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Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization

Publication ,  Conference
Roman-Vicharra, C; Chen, Y; Hu, J
Published in: MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD
September 9, 2024

Flip-flops are simultaneously endpoints of combinational logic timing paths and leaf nodes of clock networks. Hence, flip-flop placement significantly affects both circuit timing and clock network power. Previous works on flip-flop clustering/placement are mostly based on geometric models, which have limited accuracy for timing and power estimation. Moreover, these methods cannot account for the impact of clock tree synthesis parameters. In order to overcome this drawback, we develop CNN-based circuit timing and clock network power models. The CNN models are further applied to guide flip-flop centric incremental placement for simultaneous timing and clock network power optimization. Experimental results on benchmark circuits show that our method outperforms state-of-the-art previous works on timing, power, and computation runtime.

Duke Scholars

Published In

MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD

DOI

Publication Date

September 9, 2024
 

Citation

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Roman-Vicharra, C., Chen, Y., & Hu, J. (2024). Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. In MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD. https://doi.org/10.1145/3670474.3685949
Roman-Vicharra, C., Y. Chen, and J. Hu. “Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization.” In MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024. https://doi.org/10.1145/3670474.3685949.
Roman-Vicharra C, Chen Y, Hu J. Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. In: MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD. 2024.
Roman-Vicharra, C., et al. “Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization.” MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024. Scopus, doi:10.1145/3670474.3685949.
Roman-Vicharra C, Chen Y, Hu J. Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization. MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD. 2024.

Published In

MLCAD 2024 - Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD

DOI

Publication Date

September 9, 2024