Li, Z., Zheng, Q., Ku, J., Taylor, B., & Li, H. (2024). TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses. IEEE Transactions on Circuits and Systems for Artificial Intelligence, 1(1), 26–36. https://doi.org/10.1109/tcasai.2024.3452649

Li, Ziru, Qilin Zheng, Jonathan Ku, Brady Taylor, and Hai Li. “TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses.” IEEE Transactions on Circuits and Systems for Artificial Intelligence 1, no. 1 (September 2024): 26–36. https://doi.org/10.1109/tcasai.2024.3452649.

Li Z, Zheng Q, Ku J, Taylor B, Li H. TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses. IEEE Transactions on Circuits and Systems for Artificial Intelligence. 2024 Sep;1(1):26–36.

Li, Ziru, et al. “TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses.” IEEE Transactions on Circuits and Systems for Artificial Intelligence, vol. 1, no. 1, Institute of Electrical and Electronics Engineers (IEEE), Sept. 2024, pp. 26–36. Crossref, doi:10.1109/tcasai.2024.3452649.

Li Z, Zheng Q, Ku J, Taylor B, Li H. TFSRAM: A 249.8TOPS/W Timing-to-First-Spike Compute-in-Memory Neuromorphic Processing Engine With Twin-Column SRAM Synapses. IEEE Transactions on Circuits and Systems for Artificial Intelligence. Institute of Electrical and Electronics Engineers (IEEE); 2024 Sep;1(1):26–36.