First Demonstration of Positive Threshold in Dual-Gated ITO FETs with ZrO2 Dielectric

We demonstrate the first enhancement-mode dual-gated (DG) indium tin oxide (ITO) transistors with positive threshold (VTh), addressing the negative VTh challenge in amorphous oxide semiconductor (AOS) devices for monolithic 3D integration. Our novel strategy - optimized ITO stoichiometry, ZrO2 dielectrics and interface dipole engineering - overcomes top-gate-induced doping, achieving positive VTh in four gate stacks. The ZrO2 DG stack excels with record-high ION (projected 1.25 mA/μm at 20 nm), low SS (<100 mV/dec), minimal hysteresis (<11 mV), and robust stability under voltage stress and 1000 DC sweep cycles, retaining positive VTh up to 125°C. Dipole-engineered bilayers, while effective, show higher hysteresis and lower reliability. These pioneering results establish single-dielectric ZrO2 stacks as optimal for high-performance, reliable AOS logic in 3D-integrated systems.

Duke Scholars

Author Tania Roy Pierre R. Lamond Department of Electrical and Computer Engin ...