Skip to main content

Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication

Conferences
Shan, H; Guo, C; Wei, C; Cheng, F; Zhang, J; Li, HH; Chen, Y
Published in: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC
January 1, 2026

The rapid scaling of large language models demands more efficient hardware. Quantization offers a promising trade-off between efficiency and performance. With ultra-low-bit quantization, there are abundant opportunities for results reuse, and thus it can be boosted with lookup tables (LUTs) based acceleration. However, existing LUT-based methods suffer from computation and hardware overheads for LUT construction, and rely solely on bit-serial computation, which is suboptimal for ternary-weight networks. We propose Platinum, a lightweight ASIC accelerator for integer weight mixed-precision matrix multiplication (mpGEMM) using LUTs. Platinum reduces LUT construction overhead via offline-generated construction paths and supports both general bit-serial and optimized ternaryweight execution through adaptive path switching. On BitNet b1.58-3B, Platinum achieves up to 73.6 ×, 4.09 ×, and 2.15 × speedups over SpikingEyeriss, Prosperity, and 16-thread T-MAC (CPU), respectively, along with energy reductions of 32.4 ×, 3.23 ×, and 20.9 ×, all within a 0.96 mm2 chip area. This demonstrates the potential of LUT-based ASICs as efficient, scalable solutions for ultra-low-bit neural networks on edge platforms.

Duke Scholars

Altmetric Attention Stats
Dimensions Citation Stats

Published In

Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC

DOI

EISSN

2153-697X

ISSN

2153-6961

Publication Date

January 1, 2026

Start / End Page

1449 / 1455
 

Citation

APA
Chicago
ICMJE
MLA
NLM
Shan, H., Guo, C., Wei, C., Cheng, F., Zhang, J., Li, H. H., & Chen, Y. (2026). Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication. In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC (pp. 1449–1455). https://doi.org/10.1109/ASP-DAC66049.2026.11420289
Shan, H., C. Guo, C. Wei, F. Cheng, J. Zhang, H. H. Li, and Y. Chen. “Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 1449–55, 2026. https://doi.org/10.1109/ASP-DAC66049.2026.11420289.
Shan H, Guo C, Wei C, Cheng F, Zhang J, Li HH, et al. Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication. In: Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2026. p. 1449–55.
Shan, H., et al. “Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication.” Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 2026, pp. 1449–55. Scopus, doi:10.1109/ASP-DAC66049.2026.11420289.
Shan H, Guo C, Wei C, Cheng F, Zhang J, Li HH, Chen Y. Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication. Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC. 2026. p. 1449–1455.

Published In

Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC

DOI

EISSN

2153-697X

ISSN

2153-6961

Publication Date

January 1, 2026

Start / End Page

1449 / 1455