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14-bit 2.2-MS/s sigma-delta ADC's

Publication ,  Journal Article
Morizio, JC; Hoke, M; Kocak, T; Geddie, C; Hughes, C; Perry, J; Madhavapeddi, S; Hood, MH; Lynch, G; Kondoh, H; Kumamoto, T; Okuda, T ...
Published in: IEEE Journal of Solid State Circuits
July 1, 2000
Published version (DOI)

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35-mm CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections.

Duke Scholars

James Morizio
Author James Morizio Electrical and Computer Engineering

Published In

IEEE Journal of Solid State Circuits

DOI

10.1109/4.848205

ISSN

0018-9200

Publication Date

July 1, 2000

Volume

35

Issue

7

Start / End Page

968 / 976

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 1099 Other Technology
  • 0906 Electrical and Electronic Engineering
  • 0204 Condensed Matter Physics
 

Citation

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Morizio, J. C., Hoke, M., Kocak, T., Geddie, C., Hughes, C., Perry, J., … Nakaya, M. (2000). 14-bit 2.2-MS/s sigma-delta ADC's. IEEE Journal of Solid State Circuits, 35(7), 968–976. https://doi.org/10.1109/4.848205
Morizio, J. C., M. Hoke, T. Kocak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, et al. “14-bit 2.2-MS/s sigma-delta ADC's.” IEEE Journal of Solid State Circuits 35, no. 7 (July 1, 2000): 968–76. https://doi.org/10.1109/4.848205.
Morizio JC, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, et al. 14-bit 2.2-MS/s sigma-delta ADC's. IEEE Journal of Solid State Circuits. 2000 Jul 1;35(7):968–76.
Morizio, J. C., et al. “14-bit 2.2-MS/s sigma-delta ADC's.” IEEE Journal of Solid State Circuits, vol. 35, no. 7, July 2000, pp. 968–76. Scopus, doi:10.1109/4.848205.
Morizio JC, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, Madhavapeddi S, Hood MH, Lynch G, Kondoh H, Kumamoto T, Okuda T, Noda H, Ishiwaki M, Miki T, Nakaya M. 14-bit 2.2-MS/s sigma-delta ADC's. IEEE Journal of Solid State Circuits. 2000 Jul 1;35(7):968–976.

Published In

IEEE Journal of Solid State Circuits

DOI

10.1109/4.848205

ISSN

0018-9200

Publication Date

July 1, 2000

Volume

35

Issue

7

Start / End Page

968 / 976

Related Subject Headings

  • Electrical & Electronic Engineering
  • 4009 Electronics, sensors and digital hardware
  • 1099 Other Technology
  • 0906 Electrical and Electronic Engineering
  • 0204 Condensed Matter Physics