Modeling boron diffusion in thin-oxide p+ Si gate technology
Publication
, Journal Article
Fair, RB; Gafiteanu, RA
Published in: IEEE Electron Device Letters
November 1, 1996
A network defect model suitable for use in process simulation is presented for the diffusion of B in SiO
Duke Scholars
Published In
IEEE Electron Device Letters
DOI
ISSN
0741-3106
Publication Date
November 1, 1996
Volume
17
Issue
11
Start / End Page
497 / 499
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering
Citation
APA
Chicago
ICMJE
MLA
NLM
Fair, R. B., & Gafiteanu, R. A. (1996). Modeling boron diffusion in thin-oxide p+ Si gate technology. IEEE Electron Device Letters, 17(11), 497–499. https://doi.org/10.1109/55.541760
Fair, R. B., and R. A. Gafiteanu. “Modeling boron diffusion in thin-oxide p+ Si gate technology.” IEEE Electron Device Letters 17, no. 11 (November 1, 1996): 497–99. https://doi.org/10.1109/55.541760.
Fair RB, Gafiteanu RA. Modeling boron diffusion in thin-oxide p+ Si gate technology. IEEE Electron Device Letters. 1996 Nov 1;17(11):497–9.
Fair, R. B., and R. A. Gafiteanu. “Modeling boron diffusion in thin-oxide p+ Si gate technology.” IEEE Electron Device Letters, vol. 17, no. 11, Nov. 1996, pp. 497–99. Scopus, doi:10.1109/55.541760.
Fair RB, Gafiteanu RA. Modeling boron diffusion in thin-oxide p+ Si gate technology. IEEE Electron Device Letters. 1996 Nov 1;17(11):497–499.
Published In
IEEE Electron Device Letters
DOI
ISSN
0741-3106
Publication Date
November 1, 1996
Volume
17
Issue
11
Start / End Page
497 / 499
Related Subject Headings
- Applied Physics
- 4009 Electronics, sensors and digital hardware
- 0906 Electrical and Electronic Engineering