Memory controller policies for DRAM power management
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Fan, X; Ellis, CS; Lebeck, AR
Published in: Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
January 1, 2001
The increasing importance of energy efficiency has produced a multitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We develop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediately transitioning a DRAM chip to a lower power state when it becomes idle is superior to more sophisticated policies that try to predict DRAM chip idle time.
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Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
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Publication Date
January 1, 2001
Start / End Page
129 / 134
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Fan, X., Ellis, C. S., & Lebeck, A. R. (2001). Memory controller policies for DRAM power management. In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers (pp. 129–134). https://doi.org/10.1145/383082.383118
Fan, X., C. S. Ellis, and A. R. Lebeck. “Memory controller policies for DRAM power management.” In Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 129–34, 2001. https://doi.org/10.1145/383082.383118.
Fan X, Ellis CS, Lebeck AR. Memory controller policies for DRAM power management. In: Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. 2001. p. 129–34.
Fan, X., et al. “Memory controller policies for DRAM power management.” Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 2001, pp. 129–34. Scopus, doi:10.1145/383082.383118.
Fan X, Ellis CS, Lebeck AR. Memory controller policies for DRAM power management. Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. 2001. p. 129–134.
Published In
Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
DOI
Publication Date
January 1, 2001
Start / End Page
129 / 134