SNDR sensitivity analysis for cascaded ΣΔ modulators
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, Conference
Morizio, J; Hoke, M; Kocak, T; Geddie, C; Hughes, C; Perry, J; Madhavapeddi, S; Hood, M; Huffman, W; Okuda, T; Noda, H; Morimoto, Y ...
Published in: Proceedings IEEE International Symposium on Circuits and Systems
January 1, 2000
Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics will be characterized.
Duke Scholars
Published In
Proceedings IEEE International Symposium on Circuits and Systems
DOI
ISSN
0271-4310
Publication Date
January 1, 2000
Volume
3
Start / End Page
I-762-I-765
Citation
APA
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ICMJE
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Morizio, J., Hoke, M., Kocak, T., Geddie, C., Hughes, C., Perry, J., … Kondoh, H. (2000). SNDR sensitivity analysis for cascaded ΣΔ modulators. In Proceedings IEEE International Symposium on Circuits and Systems (Vol. 3, pp. I-762-I–765). https://doi.org/10.1109/ISCAS.2000.856172
Morizio, J., M. Hoke, T. Kocak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, et al. “SNDR sensitivity analysis for cascaded ΣΔ modulators.” In Proceedings IEEE International Symposium on Circuits and Systems, 3:I-762-I–765, 2000. https://doi.org/10.1109/ISCAS.2000.856172.
Morizio J, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, et al. SNDR sensitivity analysis for cascaded ΣΔ modulators. In: Proceedings IEEE International Symposium on Circuits and Systems. 2000. p. I-762-I–765.
Morizio, J., et al. “SNDR sensitivity analysis for cascaded ΣΔ modulators.” Proceedings IEEE International Symposium on Circuits and Systems, vol. 3, 2000, pp. I-762-I–765. Scopus, doi:10.1109/ISCAS.2000.856172.
Morizio J, Hoke M, Kocak T, Geddie C, Hughes C, Perry J, Madhavapeddi S, Hood M, Huffman W, Okuda T, Noda H, Morimoto Y, Kumamoto T, Ishiwaki M, Kondoh H. SNDR sensitivity analysis for cascaded ΣΔ modulators. Proceedings IEEE International Symposium on Circuits and Systems. 2000. p. I-762-I–765.
Published In
Proceedings IEEE International Symposium on Circuits and Systems
DOI
ISSN
0271-4310
Publication Date
January 1, 2000
Volume
3
Start / End Page
I-762-I-765