Spin-hall assisted STT-RAM design and discussion
Conventional spin-transfer torque random access memory (STT-RAM) is a promising technology due to its non-volatility and dense cell structure. However, the long switching time of magnetic tunneling junction (MTJ) limits the write speed of the STT-RAM. In order to improve the write performance, a Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has recently been proposed [1]. SHE effect eliminates the incubation delay existing in conventional STT-RAM switching and consequently, reduces the switching time and write energy. The corresponding read and write schemes have been also proposed [2][4]. However, the schemes in [2] suffer from a sharp writing pulse and require an external magnetic field created by a permanent magnet, introducing very high power consumption. In the design in [4], a single bit needs to be represented by two MTJs and four transistors. Such a design largely sacrifices the storage density as well as the power consumption. Nonetheless, a design that can maximize the benefits of SHE effects is still highly desired. In this work, we proposed two new memory cell designs to improve the density and power consumption of SHE-RAM while still maintaining its speed advantage.
