Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance
Publication
, Journal Article
Chen, Y; Li, H; Koh, CK; Li, J; Roy, K; Sun, G; Xie, Y
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
January 1, 2010
In this paper, we proposed a new adder design called variable-latency adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay. By applying VL-adder concept to a 64-bit carry-select adder design, more than 40% energy saving is obtained when a similar throughput is maintained. © 2010 IEEE
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Published In
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI
EISSN
1557-9999
ISSN
1063-8210
Publication Date
January 1, 2010
Volume
18
Issue
11
Start / End Page
1621 / 1624
Related Subject Headings
- Computer Hardware & Architecture
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering
- 0805 Distributed Computing
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MLA
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Chen, Y., Li, H., Koh, C. K., Li, J., Roy, K., Sun, G., & Xie, Y. (2010). Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(11), 1621–1624. https://doi.org/10.1109/TVLSI.2009.2026280
Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.
Chen Y, Li H, Koh CK, Li J, Roy K, Sun G, et al. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 Jan 1;18(11):1621–4.
Chen, Y., et al. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 11, Jan. 2010, pp. 1621–24. Scopus, doi:10.1109/TVLSI.2009.2026280.
Chen Y, Li H, Koh CK, Li J, Roy K, Sun G, Xie Y. Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010 Jan 1;18(11):1621–1624.
Published In
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOI
EISSN
1557-9999
ISSN
1063-8210
Publication Date
January 1, 2010
Volume
18
Issue
11
Start / End Page
1621 / 1624
Related Subject Headings
- Computer Hardware & Architecture
- 4009 Electronics, sensors and digital hardware
- 1006 Computer Hardware
- 0906 Electrical and Electronic Engineering
- 0805 Distributed Computing