Xin Li

Journal Article Expert Systems with Applications · July 1, 2024 Document layout analysis (DLA) is a crucial computer vision task that involves partitioning document images into high-level semantic regions such as figures, tables, backgrounds, and texts. Deep learning models for DLA typically require a large amount of l ... Full text Cite

Semi-supervised learning for explainable few-shot battery lifetime prediction

Journal Article Joule · June 19, 2024 Accurate prediction of battery lifetime is critical for ensuring timely maintenance and safety of batteries. Although data-driven methods have made significant progress, their model accuracy is often hampered by a scarcity of labeled data. To address this ... Full text Cite

Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems

Journal Article ACM Transactions on Design Automation of Electronic Systems · May 3, 2024 Root-cause analysis for integrated systems has become increasingly challenging due to their growing complexity. To tackle these challenges, machine learning (ML) has been applied to enhance root-cause analysis. Nonetheless, ML-based root-cause analysis usu ... Full text Cite

Robust battery lifetime prediction with noisy measurements via total-least-squares regression

Journal Article Integration · May 1, 2024 —Machine learning technologies have gained significant popularity in rechargeable battery research in recent years, and have been extensively adopted to construct data-driven solutions to tackle multiple challenges for energy storage in embedded computing ... Full text Cite

Potential to transform words to watts with large language models in battery research

Journal Article Cell Reports Physical Science · March 20, 2024 Conventional battery research often grapples with the challenge of accumulating scattered knowledge and information across countless academic resources, including papers, lectures, conferences, and more. This dispersed wealth of information spans a variety ... Full text Cite

Robust Sparse Recovery Based Vehicles Location Estimation in Intelligent Transportation System

Journal Article IEEE Transactions on Intelligent Transportation Systems · January 1, 2024 An architecture for vehicle position estimation is introduced in this paper to tackle the issue of vehicles positioning in traffic congestion of intelligent transportation system (ITS). The introduced architecture is related to three unmanned aerial vehicl ... Full text Cite

Status, challenges, and promises of data-driven battery lifetime prediction under cyber-physical system context

Journal Article IET Cyber-Physical Systems: Theory and Applications · January 1, 2024 Energy storage is playing an increasingly important role in the modern world as sustainability is becoming a critical issue. Within this domain, rechargeable battery is gaining significant popularity as it has been adopted to serve as the power supplier in ... Full text Cite

Drive Like a Human: Rethinking Autonomous Driving with Large Language Models

Conference Proceedings - 2024 IEEE Winter Conference on Applications of Computer Vision Workshops, WACVW 2024 · January 1, 2024 In this paper, we explore the potential of using a large language model (LLM) to understand the driving environment in a human-like manner and analyze its ability to reason, interpret, and memorize when facing complex scenarios. We argue that traditional o ... Full text Cite

Robust Wafer Classification with Imperfectly Labeled Data Based on Self-Boosting Co-Teaching

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · July 1, 2023 Wafer classification is a critical task for semiconductor manufacturing. Most conventional algorithms require a large-scale perfectly labeled dataset to train accurate classifiers. In practice, it is usually difficult or even impossible to collect perfect ... Full text Cite

Efficient Statistical Parameter Extraction for Modeling MOSFET Mismatch

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · May 1, 2023 In this article, we propose an efficient statistical parameter extraction method to accurately model the random device mismatch of MOSFETs. The key idea is to approximate the performance variations as mathematical functions of device mismatch. Based on the ... Full text Cite

Data-Driven Parameterized Corner Synthesis for Efficient Validation of Perception Systems for Autonomous Driving

Journal Article ACM Transactions on Cyber-Physical Systems · April 19, 2023 Today's automotive cyber-physical systems for autonomous driving aim to enhance driving safety by replacing the uncertainties posed by human drivers with standard procedures of automated systems. However, the accuracy of in-vehicle perception systems may s ... Full text Cite

A Blockchain-Based Certificate System with Credit Self-Adjustment

Journal Article Wuhan University Journal of Natural Sciences · April 1, 2023 Currently, digital certificate systems based on blockchain have been extensively developed and adopted. However, most of them do not take into account the certificate quality. To evaluate the credibility of certificates issued by educational institutions, ... Full text Cite

Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · February 1, 2023 Efficient high-dimensional performance modeling of analog/RF circuits over multiple corners is an important-yet-challenging task. In this article, we propose a novel performance modeling approach for analog/RF circuits, referred to as correlated Bayesian m ... Full text Cite

Unsupervised Two-Stage Root-Cause Analysis With Transfer Learning for Integrated Systems

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · February 1, 2023 The growing complexity of integrated systems makes root-cause analysis increasingly difficult. To address this challenge, advances in machine learning (ML) have been leveraged in recent years to design ML-based techniques for root-cause analysis. However, ... Full text Cite

Correlated Bayesian Co-Training for Virtual Metrology

Journal Article IEEE Transactions on Semiconductor Manufacturing · February 1, 2023 A rising challenge in manufacturing data analysis is training robust regression models using limited labeled data. In this work, we investigate a semi-supervised regression scenario, where a manufacturing process operates on multiple mutually correlated st ... Full text Cite

Machine Learning Support for Board-Level Functional Fault Diagnosis

Chapter · January 1, 2023 The ever-increasing integration density and design complexity of printed-circuit boards are making functional fault diagnosis extremely challenging. The cost associated with the testing, diagnosis and repair is one of the highest contributors to board manu ... Full text Cite

UniSeg: A Unified Multi-Modal LiDAR Segmentation Network and the OpenPCSeg Codebase

Conference Proceedings of the IEEE International Conference on Computer Vision · January 1, 2023 Point-, voxel-, and range-views are three representative forms of point clouds. All of them have accurate 3D measurements but lack color and texture information. RGB images are a natural complement to these point cloud views and fully utilizing the compreh ... Full text Cite

Robo3D: Towards Robust and Reliable 3D Perception against Corruptions

Conference Proceedings of the IEEE International Conference on Computer Vision · January 1, 2023 The robustness of 3D perception systems under natural corruptions from environments and sensors is pivotal for safety-critical applications. Existing large-scale 3D perception datasets often contain data that are meticulously cleaned. Such configurations, ... Full text Cite

DetZero: Rethinking Offboard 3D Object Detection with Long-term Sequential Point Clouds

Conference Proceedings of the IEEE International Conference on Computer Vision · January 1, 2023 Existing offboard 3D detectors always follow a modular pipeline design to take advantage of unlimited sequential point clouds. We have found that the full potential of off-board 3D detectors is not explored mainly due to two reasons: (1) the onboard multi- ... Full text Cite

LoGoNet: Towards Accurate 3D Object Detection with Local-to-Global Cross- Modal Fusion

Conference Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition · January 1, 2023 LiDAR-camera fusion methods have shown impressive performance in 3D object detection. Recent advanced multi-modal methods mainly perform global fusion, where image features and point cloud features are fused across the whole scene. Such practice lacks fine ... Full text Cite

Cross-domain document layout analysis using document style guide

Semi-supervised learning for explainable few-shot battery lifetime prediction

Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems

Robust battery lifetime prediction with noisy measurements via total-least-squares regression

Potential to transform words to watts with large language models in battery research

Robust Sparse Recovery Based Vehicles Location Estimation in Intelligent Transportation System

Status, challenges, and promises of data-driven battery lifetime prediction under cyber-physical system context

Drive Like a Human: Rethinking Autonomous Driving with Large Language Models

Robust Wafer Classification with Imperfectly Labeled Data Based on Self-Boosting Co-Teaching

Efficient Statistical Parameter Extraction for Modeling MOSFET Mismatch

Data-Driven Parameterized Corner Synthesis for Efficient Validation of Perception Systems for Autonomous Driving

A Blockchain-Based Certificate System with Credit Self-Adjustment

Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners

Unsupervised Two-Stage Root-Cause Analysis With Transfer Learning for Integrated Systems

Correlated Bayesian Co-Training for Virtual Metrology

Machine Learning Support for Board-Level Functional Fault Diagnosis

UniSeg: A Unified Multi-Modal LiDAR Segmentation Network and the OpenPCSeg Codebase

Robo3D: Towards Robust and Reliable 3D Perception against Corruptions

DetZero: Rethinking Offboard 3D Object Detection with Long-term Sequential Point Clouds

LoGoNet: Towards Accurate 3D Object Detection with Local-to-Global Cross- Modal Fusion

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · April 1, 2022 In this article, a novel asymptotic probability evaluation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate t ... Full text Cite

Fast Statistical Analysis of Rare Failure Events with Truncated Normal Distribution in High-Dimensional Variation Space

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · March 1, 2022 In this article, to accurately estimate the rare failure rates for large-scale circuits (e.g., SRAM) where process variations are modeled as truncated normal distributions in high-dimensional space, we propose a novel truncated scaled-sigma sampling (T-SSS ... Full text Cite

Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · March 1, 2022 High integration densities and design complexity make board-level functional fault diagnosis extremely difficult. Machine-learning techniques can identify functional faults with high accuracy, but they require a large volume of data to achieve high-predict ... Full text Cite

Semi-Supervised Root-Cause Analysis with Co-Training for Integrated Systems

Conference Proceedings of the IEEE VLSI Test Symposium · January 1, 2022 The increasing complexity of integrated systems has exacerbated the challenges associated with system diagnosis. To tackle these challenges, intelligent root-cause-analysis facilitated by machine learning has been proposed in recent years. However, most of ... Full text Cite

Homogeneous Multi-modal Feature Fusion and Interaction for 3D Object Detection

Conference Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) · January 1, 2022 Multi-modal 3D object detection has been an active research topic in autonomous driving. Nevertheless, it is non-trivial to explore the cross-modal feature fusion between sparse 3D points and dense 2D pixels. Recent approaches either fuse the image feature ... Full text Cite

Guest Editorial: Cloud-Edge Computing for Cyber-Physical Systems and Internet of Things

Journal Article IEEE Transactions on Industrial Informatics · November 1, 2021 Full text Cite

A Survey on Edge and Edge-Cloud Computing Assisted Cyber-Physical Systems

Journal Article IEEE Transactions on Industrial Informatics · November 1, 2021 In recent years, the investigations on cyber-physical systems (CPS) have become increasingly popular in both academia and industry. A primary obstruction against the booming deployment of CPS applications lies in how to process and manage large amounts of ... Full text Cite

Robust Classification with Noisy Labels for Manufacturing Applications: A Hybrid Approach Based on Active Learning and Data Cleaning

Conference IECON Proceedings (Industrial Electronics Conference) · October 13, 2021 Classification is an important machine learning technique that attracts growing interests in various manufacturing applications. Learning an accurate classifier generally requires a large-scale perfectly-labeled training dataset. However, such "golden"labe ... Full text Cite

Board-Level Functional Fault Identification Using Streaming Data

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · September 1, 2021 High integration densities and design complexity of printed-circuit boards make board-level functional fault identification extremely difficult. Machine learning provides an opportunity to identify functional faults with high accuracy and thereby reduce re ... Full text Cite

Unsupervised root-cause analysis with transfer learning for integrated systems

Conference Proceedings of the IEEE VLSI Test Symposium · April 25, 2021 The increasing complexity of integrated systems has exacerbated the problems associated with root-cause analysis. Leveraging advances artificial intelligence, a large amount of intelligent root-cause-analysis methods have been proposed in recent years. How ... Full text Cite

Facial Expression Recognition with Identity and Emotion Joint Learning

Journal Article IEEE Transactions on Affective Computing · April 1, 2021 Different subjects may express a specific expression in different ways due to inter-subject variabilities. In this work, besides training deep-learned facial expression feature (emotional feature), we also consider the influence of latent face identity fea ... Full text Cite

Black-Box Test-Cost Reduction Based on Bayesian Network Models

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · February 1, 2021 The growing complexity of circuit boards makes manufacturing test increasingly expensive. In order to reduce test cost, a number of test selection methods have been proposed in the literature. However, only few of these methods can be applied to black-box ... Full text Cite

Big Data for Cyber-Physical Systems

Journal Article IEEE Transactions on Big Data · December 1, 2020 Full text Cite

Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · December 1, 2020 In this article, a novel asymptotic probability approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key ... Full text Cite

Unsupervised Root-Cause Analysis for Integrated Systems

Conference Proceedings - International Test Conference · November 1, 2020 The increasing complexity and high cost of integrated systems has placed immense pressure on root-cause analysis and diagnosis. In light of artificial intelligent and machine learning, a large amount of intelligent root-cause analysis methods have been pro ... Full text Cite

Margin Guidance Network for Arbitrary-shaped Scene Text Detection

Conference Proceedings - International Conference on Tools with Artificial Intelligence, ICTAI · November 1, 2020 Segmentation-based scene text detection approaches have been adopted to arbitrary-shaped texts and have achieved a great progress. However, false detection always easily exist when the arbitrary-shaped texts are close to each other. In this paper, we propo ... Full text Cite

Exploring Inter-Sensor Correlation for Missing Data Estimation

Conference IECON Proceedings (Industrial Electronics Conference) · October 18, 2020 Data mining techniques have been widely applied to various fields including industrial, business, and governmental applications. Missing data is a common occurrence in a number of real-world databases, which may substantially affect the accuracy of data pr ... Full text Cite

Fine-grained Adaptive Testing Based on Quality Prediction

Conference ACM Transactions on Design Automation of Electronic Systems · October 1, 2020 The ever-increasing complexity of integrated circuits inevitably leads to high test cost. Adaptive testing provides an effective solution for test-cost reduction; this testing framework selects the important test items for each set of chips. However, adapt ... Full text Cite

Efficient Rare Failure Analysis over Multiple Corners via Correlated Bayesian Inference

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · October 1, 2020 In this article, we propose an efficient correlated Bayesian inference (CBI) method to estimate the system-level failure rates for large-scale circuit systems over multiple process corners. The key idea is to encode the correlations of circuit performances ... Full text Cite

A Classification Framework Using Imperfectly Labeled Data for Manufacturing Applications

Conference IEEE International Conference on Emerging Technologies and Factory Automation, ETFA · September 1, 2020 In recent years, classification techniques have been broadly adopted for a variety of smart manufacturing applications, including system health maintenance, defect detection and diagnosis, etc. However, most classification methods require a large set of tr ... Full text Cite

Efficient Classification via Partial Co-Training for Virtual Metrology

Conference IEEE International Conference on Emerging Technologies and Factory Automation, ETFA · September 1, 2020 Developing accurate and cost-effective classification techniques to facilitate virtual metrology is a critical task for modern manufacturing. In this paper, we consider the scenario in which labeling data is expensive, causing a shortage of labeled data. A ... Full text Cite

Partial Bayesian Co-training for Virtual Metrology

Journal Article IEEE Transactions on Industrial Informatics · May 1, 2020 Building accurate regression models using limited data is a challenging problem in manufacturing data analysis. In this paper, we study a particular semisupervised learning problem where labeled data are limited, while unlabeled data are plentiful. In thes ... Full text Cite

Response surface modeling

Chapter · January 1, 2020 Cite

VSB²-Net: Visual-semantic bi-branch network for zero-shot hashing

Conference Proceedings - International Conference on Pattern Recognition · January 1, 2020 Zero-shot hashing aims at learning hashing model from seen classes and the obtained model is capable of generalizing to unseen classes for image retrieval. Inspired by zero-shot learning, existing zero-shot hashing methods usually transfer the supervised k ... Full text Cite

Guest editors’ introduction: Hardware and algorithms for energy-constrained on-chip machine learning (part 2)

Journal Article ACM Journal on Emerging Technologies in Computing Systems · December 1, 2019 Full text Cite

Analog/RF post-silicon tuning via Bayesian optimization

Journal Article ACM Transactions on Design Automation of Electronic Systems · December 1, 2019 Tunable analog/RF circuit has emerged as a promising technique to address the significant performance uncertainties caused by process variations. To optimize these tunable circuits after fabrication, most existing post-silicon programming methods are devel ... Full text Cite

Computer vision algorithms and hardware implementations: A survey

Journal Article Integration · November 1, 2019 The field of computer vision is experiencing a great-leap-forward development today. This paper aims at providing a comprehensive survey of the recent progress on computer vision algorithms and their corresponding hardware implementations. In particular, t ... Full text Cite

Knowledge transfer in board-level functional fault identification using domain adaptation

Conference Proceedings - International Test Conference · November 1, 2019 High integration densities and design complexity make board-level functional fault identification extremely difficult. Machine-learning techniques can identify functional faults with high accuracy, but they require a large volume of data to achieve high pr ... Full text Cite

Track Circuit Signal Denoising Method Based on Q-Learning Algorithm

Conference 2019 IEEE Intelligent Transportation Systems Conference, ITSC 2019 · October 1, 2019 This paper presents the track circuit signal acquisition procedure and the structure of the receiving antenna. A new track circuit signal noise extraction method by adding a center tap of the receiving antenna is proposed. Furthermore, the Q-learning algor ... Full text Cite

Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · August 1, 2019 In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within loc ... Full text Cite

Guest editors' introduction to the special section on hardware and algorithms for energy-constrained on-chip machine learning

Journal Article ACM Journal on Emerging Technologies in Computing Systems · June 1, 2019 Full text Cite

Machine-Learning-Driven Matrix Ordering for Power Grid Analysis

Conference Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 · May 14, 2019 A machine-learning-driven approach for matrix ordering is proposed for power grid analysis based on domain decomposition. It utilizes support vector machine or artificial neural network to learn a classifier to automatically choose the optimal ordering alg ... Full text Cite

Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model

Conference Proceedings of the IEEE VLSI Test Symposium · April 1, 2019 The growing complexity of circuit boards makes manufacturing test increasingly expensive. In order to reduce test cost, a number of test selection methods have been proposed in the literature. However, only few of these methods can be applied to black-box ... Full text Cite

Board-Level Functional Fault Identification using Streaming Data

Conference Proceedings of the IEEE VLSI Test Symposium · April 1, 2019 High integration densities and design complexity of printed-circuit boards make board-level functional fault identification extremely difficult. Machine learning provides an opportunity to identify functional faults with high accuracy and thereby reduce re ... Full text Cite

Cross-Scale Predictive Dictionaries.

Journal Article IEEE transactions on image processing : a publication of the IEEE Signal Processing Society · February 2019 Sparse representations using data dictionaries provide an efficient model particularly for signals that do not enjoy alternate analytic sparsifying transformations. However, solving inverse problems with sparsifying dictionaries can be computationally expe ... Full text Cite

Efficient Process Variation Characterization by Virtual Probe

Chapter · January 1, 2019 In this chapter, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthrough ... Full text Cite

Fast Statistical Analysis of Rare Circuit Failure Events

Chapter · January 1, 2019 Accurately estimating the rare failure rates for nanoscale memory circuits is a challenging task, especially when the variation space is high-dimensional. In this chapter, we summarize two novel techniques to address this technical challenge. First, we des ... Full text Cite

Machine Learning in VLSI Computer-Aided Design

Book · January 1, 2019 This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the v ... Full text Cite

Introduction

Chapter · January 1, 2019 While design and implementation of autonomous and intelligent systems is not a new area, the recent advances in sensor, machine learning, and other software and hardware bring enormous opportunities as well as complexities in these systems, and they accomp ... Full text Cite

Efficient Statistical Validation of Autonomous Driving Systems

Chapter · January 1, 2019 Today’s automotive vehicles are often equipped with powerful data processing systems for driver assistance and/or autonomous driving. To meet the rigorous safety standard, ensuring extremely small failure probability over all possible operation conditions ... Full text Cite

A Preliminary Taxonomy for Machine Learning in VLSI CAD

Chapter · January 1, 2019 Machine learning is transforming many industries and areas of work, and the design of very large-scale integrated (VLSI) circuits and systems is no exception. The purpose of this book is to bring to the interested reader a cross-section of the connections ... Full text Cite

Large-Scale Circuit Performance Modeling by Bayesian Model Fusion

Chapter · January 1, 2019 In this chapter, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AM ... Full text Cite

Efficient hierarchical performance modeling for analog and mixed-signal circuits via Bayesian co-learning

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · December 1, 2018 With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We expl ... Full text Cite

Environment-Adaptable Fast Multi-Resolution (EAF-MR) optimization in large-scale RF-FPGA systems

Journal Article Eurasip Journal on Wireless Communications and Networking · December 1, 2018 Software-defined radio (SDR) can have high communication quality with a reconfigurable RF front-end. One of the main challenges of a reconfigurable RF front-end is finding an optimal configuration among all possible configurations. In order to efficiently ... Full text Cite

Model-based and data-driven approaches for building automation and control

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · November 5, 2018 Smart buildings in the future are complex cyber-physical-human systems that involve close interactions among embedded platform (for sensing, computation, communication and control), mechanical components, physical environment, building architecture, and oc ... Full text Cite

Predictive Modeling for Advanced Virtual Metrology: A Tree-Based Approach

Conference IEEE International Conference on Emerging Technologies and Factory Automation, ETFA · October 22, 2018 The rapid development of industry 4.0 has promoted the extensive adoption of big data analytics for manufacturing industry. In this domain, virtual metrology is a critical technique that is able to reduce manufacturing cost over a large amount of practical ... Full text Cite

Design Automation for Cyber-Physical Systems [Scanning the Issue]

Journal Article Proceedings of the IEEE · September 1, 2018 Cyber-physical systems (CPSs) are characterized by the seamless integration and close interaction of cyber components (e.g., sensors, computation nodes, communication networks) and physical processes (e.g., mechanical devices, physical environment, humans) ... Full text Cite

Dependable visual light-based indoor localization with automatic anomaly detection for location-based service of mobile cyber-physical systems

Journal Article ACM Transactions on Cyber-Physical Systems · August 1, 2018 Indoor localization has become popular in recent years due to the increasing need of location-based services in mobile cyber-physical systems (CPS). The massive deployment of light emitting diodes (LEDs) further promotes the indoor localization using visua ... Full text Cite

Fine-Grained Adaptive Testing Based on Quality Prediction

Conference Proceedings - International Test Conference · July 2, 2018 The ever-increasing complexity of integrated circuits inevitably leads to high test cost. Adaptive testing provides an effective solution for test-cost reduction; this testing framework selects the important test items for each set of chips. However, adapt ... Full text Cite

MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device

Conference International Conference on Digital Signal Processing, DSP · July 2, 2018 Visual object tracking (VOT) is a computer vision application and has a wide range of use. However, related state of the art algorithms using deep learning methods, are computationally intensive and storage explosive. Whats more, despite many deep learning ... Full text Cite

Guest editors' introduction: Frontiers of hardware and algorithms for on-chip learning

Journal Article ACM Journal on Emerging Technologies in Computing Systems · July 1, 2018 Full text Cite

Single-Channel Real-Time Drowsiness Detection Based on Electroencephalography.

Conference Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference · July 2018 The need of a reliable drowsiness detection system is arising today, as drowsiness is considered as a major cause for accidents as much as alcohol. In this paper, we propose a real-time drowsiness detection algorithm based on a single-channel electroenceph ... Full text Cite

An efficient audio based performance evaluation system for computer assisted piano learning

Conference ICNC-FSKD 2017 - 13th International Conference on Natural Computation, Fuzzy Systems and Knowledge Discovery · June 21, 2018 In this paper, we propose an audio based piano performance evaluation system for piano learning, aiming at giving objective feedbacks to the piano beginners so that their self-practicing could be more efficient. We target to build a system which could eval ... Full text Cite

Improving Diagnostic Resolution of Failing ICs Through Learning

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · June 1, 2018 Diagnosis is the first analysis step for uncovering the root cause of failure for a defective integrated logic circuit. The conventional objective of identifying failure locations has been augmented with various physically-aware diagnosis techniques that a ... Full text Cite

Identifying wafer-level systematic failure patterns via unsupervised learning

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · April 1, 2018 In this paper, we propose a novel methodology for detecting systematic failure patterns at the wafer level for yield learning. Our proposed methodology takes the binary testing results (i.e., pass or fail) of all dies over multiple wafers, cluster these wa ... Full text Cite

Intelligent corner synthesis via cycle-consistent generative adversarial networks for efficient validation of autonomous driving systems

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · February 20, 2018 Today's automotive vehicles are often equipped with powerful data processing systems for driver assistance and/or autonomous driving. To meet the rigorous safety standard, one critical task is to ensure extremely small failure rate over all possible operat ... Full text Cite

Message from the general chairs

Conference Proceedings - 2017 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017 · February 15, 2018 Full text Cite

Impact of circuit-level non-idealities on vision-based autonomous driving systems

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 13, 2017 We describe a novel methodology to validate vision-based autonomous driving systems over different circuit corners with consideration of temperature variation and circuit aging. The proposed work is motivated by the fact that low-level circuit implementati ... Full text Cite

Efficient programming of reconfigurable radio frequency (RF) systems

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 13, 2017 Reconfigurable radio frequency (RF) system has recently emerged as a promising solution to cope with multiple communication standards and high spectrum density. In this paper, we propose a novel optimization framework to efficiently program a reconfigurabl ... Full text Cite

Algorithm and hardware implementation for visual perception system in autonomous vehicle: A survey

Journal Article Integration, the VLSI Journal · September 1, 2017 This paper briefly surveys the recent progress on visual perception algorithms and their corresponding hardware implementations for the emerging application of autonomous driving. In particular, vehicle and pedestrian detection, lane detection and drivable ... Full text Cite

A configurable nonlinear operation unit for neural network accelerator

Conference Proceedings of International Conference on ASIC · July 1, 2017 With the development of machine learning, neural network accelerators are widely used to speed up the calculation. Many of the accelerators are designed to be configurable so they can be widely used in different situations. Nonlinear operation is essential ... Full text Cite

A high utilization FPGA-based accelerator for variable-scale convolutional neural network

Conference Proceedings of International Conference on ASIC · July 1, 2017 Convolutional Neural Network (CNN) plays an essential role in computer vision applications for high classification accuracy and robust generalization capability. In recent years, various GPU-based or application-specific hardware approaches have been propo ... Full text Cite

Process optimization of inductively coupled plasma etching for large aspect ratio silicon nanopillars

Journal Article Qiangjiguang Yu Lizishu/High Power Laser and Particle Beams · July 1, 2017 Deep Reactive Ion Etching (DRIE) process on Si to achieve nanopillar arrays with large aspect ratio by using hydrogen silsesquioxane (HSQ) as etching masks has been systematically studied. Parameters in etching process such as coil power, platen power and ... Full text Cite

Partial Co-training for virtual metrology

Conference IEEE International Conference on Emerging Technologies and Factory Automation, ETFA · June 28, 2017 Virtual metrology is an important tool for industrial automation. To accurately build regression models for virtual metrology, we consider semi-supervised learning where labeled data are expensive to collect, but unlabeled data are abundant. In such a scen ... Full text Cite

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation

Conference Proceedings - Design Automation Conference · June 18, 2017 In this paper, a novel Asymptotic Probability Estimation (APE) method is proposed to estimate the probability of correlated rare failure events for complex integrated systems containing a large number of replicated cells. The key idea is to approximate the ... Full text Cite

Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning

Conference Proceedings - Design Automation Conference · June 18, 2017 With the continuous drive towards integrated circuits scaling, efficient performance modeling is becoming more crucial yet, more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We ex ... Full text Cite

Compressive spectral anomaly detection

Conference 2017 IEEE International Conference on Computational Photography, ICCP 2017 - Proceedings · June 16, 2017 We propose a novel compressive imager for detecting anomalous spectral profiles in a scene. We model the background spectrum as a low-dimensional subspace while assuming the anomalies to form a spatially-sparse set of spectral profiles different from the b ... Full text Cite

C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · June 1, 2017 Parametric yield estimation is a critical task for design and validation of analog and mixed-signal (AMS) circuits. However, the computational cost for yield estimation based on Monte Carlo (MC) analysis is often prohibitively high, especially when multipl ... Full text Cite

Training fixed-point classifiers for on-chip low-power implementation

Journal Article ACM Transactions on Design Automation of Electronic Systems · June 1, 2017 In this article, we develop several novel algorithms to train classifiers that can be implemented on chip with low-power fixed-point arithmetic with extremely small word length. These algorithms are based on Linear Discriminant Analysis (LDA), Support Vect ... Full text Cite

Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing

Journal Article IEEE Transactions on Nanotechnology · May 1, 2017 Full text Cite

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares

Chapter · April 19, 2017 Full text Cite

Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing.

Journal Article IEEE transactions on biomedical circuits and systems · April 2017 Compressive sensing is widely used in biomedical applications, and the sampling matrix plays a critical role on both quality and power consumption of signal acquisition. It projects a high-dimensional vector of data into a low-dimensional subspace by matri ... Full text Cite

An FPGA-Based Hardware Accelerator for Traffic Sign Detection

Journal Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems · April 1, 2017 Traffic sign detection plays an important role in a number of practical applications, such as intelligent driver assistance and roadway inventory management. In order to process the large amount of data from either real-time videos or large off-line databa ... Full text Cite

High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis

Journal Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems · March 1, 2017 The failure rate of static RAM (SRAM) cells is restricted to be extremely low to ensure sufficient high yield for the entire chip. In addition, multiple performances of interest and influences from peripherals make SRAM failure rate estimation a high-dimen ... Full text Cite

Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · March 1, 2017 Power supply fluctuation can be potential threat to the correct operations of processors, in the form of voltage emergency that happens when supply voltage drops below a certain threshold. Noise sensors (with either analog or digital outputs) can be placed ... Full text Cite

DFM evaluation using IC diagnosis data

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · March 1, 2017 Design for manufacturability rule evaluation using manufactured silicon (DREAMS) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of design for manufacturability (DFM) rules using the results of logic diagnosis perfo ... Full text Cite

Guest editors' introduction: Hardware and algorithms for on-chip learning

Journal Article ACM Journal on Emerging Technologies in Computing Systems · February 1, 2017 Full text Cite

Relay participated-new-type building energy management system: An energy-efficient routing scheme for wireless sensor network-based building energy management systems

Journal Article International Journal of Distributed Sensor Networks · January 1, 2017 With the development of wireless sensor networks, many building energy management systems are getting to adopt wireless sensor network as their communication infrastructure. However, the existing wireless sensor network protocols cannot satisfy the energy- ... Full text Cite

Energy Storage Sizing Taking Into Account Forecast Uncertainties and Receding Horizon Operation

Journal Article IEEE Transactions on Sustainable Energy · January 1, 2017 Energy storage systems (ESS) have the potential to be very beneficial for applications such as reducing the ramping of generators, peak shaving, and balancing not only the variability introduced by renewable energy sources, but also the uncertainty introdu ... Full text Cite

Guest editorial: Special issue on smart homes, buildings and infrastructures

Journal Article ACM Transactions on Cyber-Physical Systems · January 1, 2017 Full text Cite

An audio based piano performance evaluation method using deep neural network based acoustic modeling

Conference Proceedings of the Annual Conference of the International Speech Communication Association, INTERSPEECH · January 1, 2017 In this paper, we propose an annotated piano performance evaluation dataset with 185 audio pieces and a method to evaluate the performance of piano beginners based on their audio recordings. The proposed framework includes three parts: piano key posterior ... Full text Cite

Aggregated load and generation equivalent circuit models with semi-empirical data fitting

Conference 2016 IEEE Green Energy and Systems Conference, IGSEC 2016 · December 16, 2016 In this paper we propose a semi-empirical modeling framework for aggregated electrical load and generation using an equivalent circuit formulation. The proposed models are based on complex rectangular voltage and current state variables that provide a gene ... Full text Cite

Unified power system analyses and models using equivalent circuit formulation

Conference 2016 IEEE Power and Energy Society Innovative Smart Grid Technologies Conference, ISGT 2016 · December 9, 2016 In this paper we propose and demonstrate the potential for unifying models and algorithms for the steady state and transient simulation of single-phase and three-phase power systems. At present, disparate algorithms and models are used for the different an ... Full text Cite

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · December 1, 2016 Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performanc ... Full text Cite

Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · November 7, 2016 In this paper, a novel Asymptotic Probability Approximation (APA) method is proposed to estimate the overall rare probability of correlated failure events for complex circuits containing a large number of replicated cells (e.g., SRAM bit-cells). The key id ... Full text Cite

Efficient statistical validation of machine learning systems for autonomous driving

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · November 7, 2016 Today's automotive industry is making a bold move to equip vehicles with intelligent driver assistance features. A modern automobile is now equipped with a powerful computing platform to run multiple machine learning algorithms for environment perception ( ... Full text Cite

Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD

Journal Article IEEE Design and Test · October 1, 2016 Full text Cite

Overview of cyber-physical temperature estimation in smart buildings: From modeling to measurements

Conference Proceedings - IEEE INFOCOM · September 6, 2016 Smart buildings are playing a more important role in everyday lives of people. One important goal of creating smart buildings is to offer highly comfortable services to the occupants at the lowest cost. In-building temperature modeling and measurement is a ... Full text Cite

Message from the general chairs

Conference Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI · September 2, 2016 Full text Cite

Overview of Circuits, Systems, and Applications of Spintronics

Journal Article IEEE Journal on Emerging and Selected Topics in Circuits and Systems · September 1, 2016 Spintronic technologies have demonstrated significant promise due to multitude of features that can find applications in storage, cache, non-volatile combinational logic, sequential logic, search engines, security primitives, and, neuro-inspired computing ... Full text Cite

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue)

Journal Article IEEE Journal on Emerging and Selected Topics in Circuits and Systems · September 1, 2016 Full text Cite

Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · September 1, 2016 The random telegraph noise (RTN) is becoming more serious in advanced technologies. Due to the unpredictability of the physical phenomenon, RTN is a good randomness source for true random number generators (TRNG). In this paper, we build fundamental random ... Full text Cite

Cross-scale predictive dictionaries for image and video restoration

Conference Proceedings - International Conference on Image Processing, ICIP · August 3, 2016 We propose a novel signal model, based on sparse representations, that captures cross-scale features for visual signals. We show that cross-scale predictive model enables faster solutions to sparse approximation problems. This is achieved by first solving ... Full text Cite

Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · August 1, 2016 Efficient performance modeling of today's analog and mixed-signal circuits is an important yet challenging task, due to the high-dimensional variation space and expensive circuit simulation. In this paper, we propose a novel performance modeling algorithm ... Full text Cite

Identifying systematic spatial failure patterns through wafer clustering

Conference Proceedings - IEEE International Symposium on Circuits and Systems · July 29, 2016 In this paper, we propose a novel methodology for detecting systematic spatial failure patterns at wafer level for yield learning. Our proposed methodology takes the testing results (i.e., pass or fail) of a number of dies over different wafers, cluster al ... Full text Cite

Virtual temperature measurement for smart buildings via Bayesian model fusion

Conference Proceedings - IEEE International Symposium on Circuits and Systems · July 29, 2016 One important goal of creating smart buildings is to offer highly comfortable services to the occupants at low cost. Real-time temperature measurement and monitoring is a critical task to facilitate high-quality service with low energy consumption and, hen ... Full text Cite

Weight-based link scheduling for convergecast in WirelessHART network

Journal Article International Journal of Distributed Sensor Networks · July 22, 2016 WirelessHART is considered to be one of the most promising wireless network protocols for its high robustness comparing to other similar wireless networks. Convergecast is an efficient approach for industrial control. But in WirelessHART specifications, no ... Full text Cite

An equivalent circuit formulation for three-phase power flow analysis of distribution systems

Conference Proceedings of the IEEE Power Engineering Society Transmission and Distribution Conference · July 22, 2016 In this paper, we describe a power flow formulation for 3-phase distribution systems that is based on an equivalent circuit model. It is shown that this physical model based solution is able to accommodate a wide range of complex and unbalanced loads witho ... Full text Cite

Improving robustness and modeling generality for power flow analysis

Conference Proceedings of the IEEE Power Engineering Society Transmission and Distribution Conference · July 22, 2016 In this paper we present an equivalent circuit model for power system networks that facilitates robust and efficient AC power flow simulation and enables the incorporation of more generalized bus and line models. The circuit equations are formulated in ter ... Full text Cite

Steady-state analysis of power system harmonics using equivalent split-circuit models

Conference IEEE PES Innovative Smart Grid Technologies Conference Europe · July 2, 2016 In this paper we introduce a novel algorithm for harmonic steady-state analysis of power systems that is based on the equivalent split-circuit models recently introduced for power flow analysis. By using an equivalent circuit with current and voltage as th ... Full text Cite

Diagnostic resolution improvement through learning-guided physical failure analysis

Conference Proceedings - International Test Conference · July 2, 2016 An accurate and high-resolution diagnosis enables physical failure analysis (PFA) to identify and understand the root-cause of integrated-circuit failure. Despite many existing techniques for improving diagnosis, resolution is still far from ideal, which h ... Full text Cite

Correlated Bayesian Model Fusion: Efficient performance modeling of large-scale tunable analog/RF integrated circuits

Conference Proceedings - Design Automation Conference · June 5, 2016 Tunable circuit has emerged as a promising methodology to address the grand challenge posed by process variations. Efficient high-dimensional performance modeling of tunable analog/RF circuits is an important yet challenging task. In this paper, we propose ... Full text Cite

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue)

Journal Article IEEE Journal on Emerging and Selected Topics in Circuits and Systems · June 1, 2016 Full text Cite

Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · June 1, 2016 In this paper, we propose a novel spatial variation modeling method based on hidden Markov tree (HMT) for nanoscale integrated circuits, which could efficiently improve the accuracy of full-wafer/chip spatial variations recovery at extremely low measuremen ... Full text Cite

Statistical rare-event analysis and parameter guidance by elite learning sample selection

Journal Article ACM Transactions on Design Automation of Electronic Systems · May 27, 2016 Accurately estimating the failure region of rare events for memory-cell and analog circuit blocks under process variations is a challenging task. In this article, we propose a new statistical method, called EliteScope, to estimate the circuit failure rates ... Full text Cite

Efficient analog circuit optimization using sparse regression and error margining

Conference Proceedings - International Symposium on Quality Electronic Design, ISQED · May 25, 2016 In this paper, we propose a novel analog circuit optimization methodology for achieving high parametric yield. We solve the statistical worst-case optimization problem by a sequence of linear programings where performance metrics are fitted using sparse re ... Full text Cite

Energy-constrained distributed learning and classification by exploiting relative relevance of sensors' data

Journal Article IEEE Journal on Selected Areas in Communications · May 1, 2016 We consider the problem of communicating data from energy-constrained distributed sensors. To reduce energy requirements, we go beyond the source reconstruction problem classically addressed, and focus on the problem where the recipient wants to perform su ... Full text Cite

Efficient spatial variation modeling via robust dictionary learning

Conference Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 · April 25, 2016 In this paper, we propose a novel spatial variation modeling method based on robust dictionary learning for nanoscale integrated circuits. This method takes advantage of the historical data to efficiently improve the accuracy of wafer-level spatial variati ... Full text Cite

Parasitic-aware common-centroid FinFET placement and routing for current-ratio matching

Conference ACM Transactions on Design Automation of Electronic Systems · April 1, 2016 The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process v ... Full text Cite

Energy efficient learning and classification for distributed sensing

Conference 2016 8th International Conference on Communication Systems and Networks, COMSNETS 2016 · March 23, 2016 In order to reduce total energy communicated by distributed sensors, we address the problem where the recipient wants to perform supervised learning and classification on the data received from the sensors. Restricting our attention to a noiseless communic ... Full text Cite

Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · March 7, 2016 Reconfigurable radio frequency (RF) system has emerged as a promising avenue to achieve high communication performance while adapting to versatile commercial wireless environment. In this paper, we propose a novel technique to optimally program a reconfigu ... Full text Cite

Thermal modeling for energy-efficient smart building with advanced overfitting mitigation technique

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · March 7, 2016 Building energy accounts large amount of the total energy consumption, and smart building energy control leads to high energy efficiency and significant energy savings. A compact and accurate building thermal model is important for designing the efficient ... Full text Cite

Distributed MPC for Efficient Coordination of Storage and Renewable Energy Sources Across Control Areas

Journal Article IEEE Transactions on Smart Grid · March 1, 2016 In electric power systems, multiple entities are responsible for ensuring an economic and reliable way of delivering power from producers to consumers. With the increase of variable renewable generation it is becoming increasingly important to take advanta ... Full text Cite

Statistical rare event analysis using smart sampling and parameter guidance

Conference International System on Chip Conference · February 12, 2016 In this paper, we propose a new efficient statistical method for failure probability estimation of analog circuits with rate failure events, which is a time-consuming process using the existing Monte Carlo method. On top of this, the new method can also pr ... Full text Cite

Co-Learning Bayesian Model Fusion: Efficient performance modeling of analog and mixed-signal circuits using side information

Conference 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 · January 5, 2016 Efficient performance modeling of today's analog and mixed-signal (AMS) circuits is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is referred to as Co-Learning Bayesian Model Fusion (CL-BMF). The k ... Full text Cite

From robust chip to smart building: CAD algorithms and methodologies for uncertainty analysis of building performance

Conference 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 · January 5, 2016 Buildings consume about 40% of the total energy use in the U.S. and, hence, accurately modeling, analyzing and optimizing building energy is considered as an extremely important task today. Towards this goal, uncertainty/sensitivity analysis has been propo ... Full text Cite

Learning based compact thermal modeling for energy-efficient smart building management

Conference 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 · January 5, 2016 In this article, we propose a new behavioral thermal modeling method for fast building performance analysis, which is critical for energy-efficient smart building control and management. The new approach is based on two recurrent neutral network architectu ... Full text Cite

Statistical learning in chip (SLIC)

Conference 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 · January 5, 2016 Despite best efforts, integrated systems are born (manufactured) with a unique 'personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possi ... Full text Cite

Energy-efficient wireless temperature sensoring for smart building applications

Conference 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings · January 1, 2016 Building energy accounts for large amount of the total energy consumption, and smart building energy control leads to high energy efficiency and significant energy savings. For energy-efficient smart building applications, accurate and robust measurement o ... Full text Cite

Self-healing analog/RF circuits

Chapter · January 1, 2016 Process variation is the most critical issue for the nanoscale analog and radiofrequency integrated circuits (ICs). There are many traditional techniques to mitigate the process variations problems which are mainly based on some form of static approach. Ho ... Full text Cite

Efficient Performance Modeling via Dual-Prior Bayesian Model Fusion for Analog and Mixed-Signal Circuits

Conference Proceedings - Design Automation Conference · January 1, 2016 In this paper, we propose a novel Dual-Prior Bayesian Model Fusion (DP-BMF) algorithm for performance modeling. Different from the previous BMF methods which use only one source of prior knowledge, DP-BMF takes advantage of multiple sources of prior knowle ... Full text Cite

Efficient Performance Modeling of Analog Integrated Circuits via Kernel Density Based Sparse Regression

Conference Proceedings - Design Automation Conference · January 1, 2016 With the aggressive scaling of integrated circuit technology, analog performance modeling is facing enormous challenges due to high-dimensional variation space and expensive transistor-level simulation. In this paper, we propose a kernel density based spar ... Full text Cite

Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · January 1, 2016 Efficiently optimizing large-scale, complex analog systems requires to know the performance tradeoffs for various analog circuit blocks. In this paper, we propose a radically new approach for analog performance tradeoff modeling. Our key idea is to broadly ... Full text Cite

Decoding Brain States Based on Magnetoencephalography From Prespecified Cortical Regions.

Journal Article IEEE transactions on bio-medical engineering · January 2016 Brain state decoding based on whole-head MEG has been extensively studied over the past decade. Recent MEG applications pose an emerging need of decoding brain states based on MEG signals originating from prespecified cortical regions. Toward this goal, we ... Full text Cite

A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost

Conference Proceedings - 2016 IEEE Biomedical Circuits and Systems Conference, BioCAS 2016 · January 1, 2016 A 16-channel, low-complexity and energy-efficient electroencephalography (EEG) processor for patient-specific seizure detection is presented. The feature extraction algorithm extracts line length features from approximation coefficients from a low-overhead ... Full text Cite

A 18mW, 3.3dB NF, 60GHz LNA in 32nm SOI CMOS technology with autonomic NF calibration

Conference Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium · November 25, 2015 A self-healing mmWave SoC integrating an 8052 microcontroller with 12kB of memory, an ADC, a temperature sensor, and a 3-stage cascode 60GHz LNA, implemented in a 32nm SOI CMOS technology exhibits a peak gain of 21dB, an average 3.3dB NF from 53 to 62GHz a ... Full text Cite

Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation space

Conference Proceedings of the Custom Integrated Circuits Conference · November 25, 2015 Accurately estimating the rare failure events of nanoscale ICs in a high-dimensional variation space is extremely challenging. In this paper, we propose a novel Bayesian scaled-sigma sampling (BSSS) technique to address this technical challenge. BSSS can b ... Full text Cite

A robust and efficient power series method for tracing PV curves

Conference 2015 North American Power Symposium, NAPS 2015 · November 20, 2015 Estimating the voltage collapse point of a power grid is an important problem in power flow analysis. In this paper, we propose a novel power series method (PSM) for tracing the power-voltage (PV) curve and estimating the collapse point. By expanding the p ... Full text Cite

An equivalent circuit formulation of the power flow problem with current and voltage state variables

Conference 2015 IEEE Eindhoven PowerTech, PowerTech 2015 · August 31, 2015 Steady state analysis of power grids is typically performed using power flow analysis, where nonlinear balance equations of real and reactive power are solved to calculate the voltage magnitude, phase, and power at every bus. Transient analysis of the same ... Full text Cite

Vortex: Variation-aware training for memristor X-bar

Conference Proceedings - Design Automation Conference · July 24, 2015 Recent advances in development of memristor devices and cross-bar integration allow us to implement a low-power on-chIP neuromorphic computing system (NCS) with small footprint. Training methods have been proposed to program the memristors in a crossbar by ... Full text Cite

An EDA framework for large scale hybrid neuromorphic computing systems

Conference Proceedings - Design Automation Conference · July 24, 2015 In implementations of neuromorphic computing systems (NCS), memristor and its crossbar topology have been widely used to realize fully connected neural networks. However, many neural networks utilized in real applications often have a sparse connectivity, ... Full text Cite

MTunes: Efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process

Conference Proceedings - Design Automation Conference · July 24, 2015 Uncertainty prevails in IC manufacturing and circuit operation. In particular, process variability has a huge impact on circuit performance, especially for mixed-signal/RF circuits, leading to unacceptable yields. Additionally, environmental uncertainties, ... Full text Cite

Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · July 1, 2015 Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., static random-access memory, D flip-flop, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma ... Full text Cite

Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits

Conference Proceedings - Design Automation Conference · June 7, 2015 A critical-yet-challenging problem of analog/mixed-signal circuit validation in either pre-silicon or post-silicon stage is to estimate the parametric yield of the performances. In this paper, we propose a novel Bayesian model fusion method for efficient m ... Full text Cite

Feasibility study of a dual-gate photosensitive thin-film transistor for fingerprint sensor integrated active-matrix display

Conference Digest of Technical Papers - SID International Symposium · June 1, 2015 By placing a transparent conductive ITO layer atop a display driver thin-film transistor (TFT), a dual-gate photosensitive TFT is formed to integrate a fingerprint sensing function in a display pixel An analytical model is proposed to elaborate its working ... Full text Cite

EDA challenges for memristor-crossbar based neuromorphic computing

Conference Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI · May 20, 2015 The increasing gap between the high data processing capability of modern computing systems and the limited memory bandwidth motivated the recent significant research on neuromorphic computing systems (NCS), which are inspired from the working mechanism of ... Full text Cite

A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits

Conference Proceedings -Design, Automation and Test in Europe, DATE · April 22, 2015 In this paper, we adopt a novel numerical algorithm, referred to as dual augmented Lagrangian method (DALM), for efficient test cost reduction based on spatial variation modeling. The key idea of DALM is to derive the dual formulation of the L1-regularized ... Full text Cite

Efficient bit error rate estimation for high-speed link by Bayesian model fusion

Conference Proceedings -Design, Automation and Test in Europe, DATE · April 22, 2015 High-speed I/O link is an important component in computer systems, and estimating its bit error rate (BER) is a critical task to guarantee its performance. In this paper, we propose an efficient method to estimate BER by Bayesian Model Fusion. Its key idea ... Full text Cite

Fast deployment of alternate analog test using Bayesian model fusion

Conference Proceedings -Design, Automation and Test in Europe, DATE · April 22, 2015 In this paper, we address the problem of limited training sets for learning the regression functions in alternate analog test. Typically, a large volume of real data needs to be collected from different wafers and lots over a long period of time to be able ... Full text Cite

Common-centroid FinFET placement considering the impact of gate misalignment

Conference Proceedings of the International Symposium on Physical Design · March 29, 2015 The FinFET technology has been regarded as a better alternative among different device technologies at 22nm node and beyond due to more effective channel control and lower power consumption. However, the gate misalignment problem resulting from process var ... Full text Cite

SIPredict: Efficient post-layout waveform prediction via System Identification

Conference 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 · March 11, 2015 In this paper, we propose a post-layout waveform prediction method by System Identification (SI) based on the fact that the waveforms of pre-layout and post-layout are always correlated. Mathematical models are built to describe the relationships between t ... Full text Cite

Fast statistical analysis of rare failure events for memory circuits in high-dimensional variation space

Conference 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 · March 11, 2015 Accurately estimating the rare failure rates for nanoscale memory circuits is a challenging task, especially when the variation space is high-dimensional. In this paper, we summarize two novel techniques to address this technical challenge. First, we descr ... Full text Cite

Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data

Conference 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 · March 11, 2015 Passive macromodeling for RF circuit blocks is a critical task to facilitate efficient system-level simulation for large-scale RF systems (e.g., wireless transceivers). In this paper we propose a novel algorithm to find the optimal macromodel that minimize ... Full text Cite

Efficient transient analysis of power delivery network with clock/power gating by sparse approximation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · March 1, 2015 Transient analysis of large-scale power delivery network (PDN) is a critical task to ensure the functional correctness and desired performance of today's integrated circuits (ICs), especially if significant transient noises are induced by clock and/or powe ... Full text Cite

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Conference Proceedings - International Test Conference · February 6, 2015 In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on wafer-level spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the ... Full text Cite

SLIC: Statistical learning in chip

Conference Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 · February 2, 2015 Despite best efforts, integrated systems are 'born' (manufactured) with a unique 'personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is pos ... Full text Cite

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares

Conference Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 · February 2, 2015 To reduce healthcare cost while simultaneously delivering high-quality health services, developing new portable and/or implantable biomedical devices is of great importance for both health monitoring and clinical treatment. In this paper, we describe a rad ... Full text Cite

A novel analog physical synthesis methodology integrating existent design expertise

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · February 1, 2015 Analog layout design has been a manual, time-consuming, and error-prone task for decades. To speed up layout design time for a new design, analog layout designers prefer referring to legacy designs and layouts rather than starting from scratch, or thorough ... Full text Cite

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 5, 2015 Neuromorphic computing system (NCS) is a promising architecture to combat the well-known memory bottleneck in Von Neumann architecture. The recent breakthrough on memristor devices made an important step toward realizing a low-power, small-footprint NCS on ... Full text Cite

MPME-DP: Multi-population moment estimation via dirichlet process for efficient validation of analog/mixed-signal circuits

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 5, 2015 Moment estimation is one of the most important tasks to appropriately characterize the performance variability of today's nanoscale integrated circuits. In this paper, we propose an efficient algorithm of multi-population moment estimation via Dirichlet Pr ... Full text Cite

Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 5, 2015 In this paper, we propose a novel subset simulation (SUS) technique to efficiently estimate the rare failure rate for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) in high-dimensional variation space. The key idea of SUS is to express the rare failure p ... Full text Cite

Phase noise impairment and environment-adaptable fast (EAF) optimization for programming of reconfigurable radio frequency (RF) receivers

Conference Proceedings - IEEE Global Communications Conference, GLOBECOM · January 1, 2015 In order to support a multi-standard platform, a reconfigurable RF front-end needs an optimal configuration that adapts to a dynamic communication condition. To find an optimal configuration efficiently, we previously proposed the Environment-Adaptable Fas ... Full text Cite

A statistical methodology for noise sensor placement and full-chIP voltage map generation

Conference Proceedings - Design Automation Conference · January 1, 2015 © 2015 ACM. Noise margin violation, also known as voltage emergency induced by continuously reducing noise margin and increasing magnitude of current swings, is becoming a severe threat to the correct execution of applications in processors. Noise sensors ... Full text Cite

Optimal storage sizing using two-stage stochastic optimization for intra-hourly dispatch

Conference 2014 North American Power Symposium, NAPS 2014 · November 21, 2014 With the increasing penetration of renewable energy sources into the electric power grid, a heightened amount of attention is being given to the topic of energy storage, a popular solution to account for the variability of these sources. Energy storage sys ... Full text Cite

Environment-adaptable efficient optimization for programming of reconfigurable radio frequency (RF) receivers

Conference Proceedings - IEEE Military Communications Conference MILCOM · November 13, 2014 Software defined radio has been developed for supporting multi-standard radio receivers, but remains vulnerable to interference. In order to overcome this interference challenge, this paper proposes replacing the fixed wide-band Radio Frequency (RF) front- ... Full text Cite

Toward efficient programming of reconfigurable radio frequency (RF) receivers

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · March 27, 2014 Reconfigurable radio frequency (RF) system is an emerging component to mitigate the growing engineering cost for wireless chip design. In this paper, we propose a new methodology for efficient programming of reconfigurable RF receiver. The proposed method ... Full text Cite

Joint invariant estimation of RF impairments for reconfigurable Radio Frequency(RF) front-end

Conference 2014 IEEE Globecom Workshops, GC Wkshps 2014 · March 18, 2014 To support a multi-standard platform using Software Defined Radio (SDR), reconfigurable Radio Frequency (RF) front-ends have recently been proposed as a more reliable front-end than the currently used fixed wide-band RF front-ends. With these reconfigurabl ... Full text Cite

Using relative-relevance of data pieces for efficient communication, with an application to Neural data acquisition

Conference 2014 52nd Annual Allerton Conference on Communication, Control, and Computing, Allerton 2014 · January 30, 2014 In this paper, we consider the problem of communicating data from distributed sensors for the goal of inference. Two inference problems of linear regression and binary linear classification are investigated. Assuming perfect training of the classifier, an ... Full text Cite

DALM-SVD: Accelerated sparse coding through singular value decomposition of the dictionary

Conference 2014 IEEE International Conference on Image Processing, ICIP 2014 · January 28, 2014 Sparse coding techniques have seen an increasing range of applications in recent years, especially in the area of image processing. In particular, sparse coding using ℓ1-regularization has been efficiently solved with the Augmented Lagrangian (AL) applied ... Full text Cite

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

Conference Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference · January 2014 This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosi ... Full text Cite

Adaptive circuit design methodology and test applied to millimeter-wave circuits

Journal Article IEEE Design and Test · January 1, 2014 A theoretical framework is proposed that allows the prediction of RF and mm-wave circuit performance with on-chip sensors through the use of indirect sensing with Bayesian model fusion (BMF) instead of through costly and difficult direct integrated measure ... Full text Cite

Indirect performance sensing for on-chip self-healing of analog and RF circuits

Journal Article IEEE Transactions on Circuits and Systems I: Regular Papers · January 1, 2014 The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuits increasingly susceptible to large-scale process variations. On-chip self-healing has been proposed as a promising remedy to address the variability ... Full text Cite

Verification based ECG biometrics with cardiac irregular conditions using heartbeat level and segment level information fusion

Conference ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings · January 1, 2014 We propose an ECG based robust human verification system for both healthy and cardiac irregular conditions using the heartbeat level and segment level information fusion. At the heartbeat level, we first propose a novel beat normalization and outlier remov ... Full text Cite

Computer-aided design of machine learning algorithm: Training fixed-point classifier for on-chip low-power implementation

Conference Proceedings - Design Automation Conference · January 1, 2014 In this paper, we propose a novel linear discriminant analysis algorithm, referred to as LDA-FP, to train on-chip classifiers that can be implemented with low-power fixed-point arithmetic with extremely small word length. LDA-FP incorporates the nonidealit ... Full text Cite

Multiple-population moment estimation: Exploiting interpopulation correlation for efficient moment estimation in analog/mixed-signal validation

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · January 1, 2014 Moment estimation is an important problem during circuit validation, in both presilicon and postsilicon stages. From the estimated moments, the probability of failure and parametric yield can be estimated at each circuit configuration and corner, and these ... Full text Cite

BMF-BD: Bayesian model fusion on bernoulli distribution for efficient yield estimation of integrated circuits

Conference Proceedings - Design Automation Conference · January 1, 2014 Accurate yield estimation is one of the important yet challenging tasks for both pre-silicon verification and post-silicon validation. In this paper, we propose a novel method of Bayesian model fusion on Bernoulli distribution (BMF-BD) for efficient yield ... Full text Cite

Bayesian Model Fusion: A statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2013 In this paper, we describe a novel statistical framework, referred to as Bayesian Model Fusion (BMF), that allows us to minimize the simulation and/or measurement cost for both pre-silicon validation and post-silicon tuning of analog and mixed-signal (AMS) ... Full text Cite

DREAMS: DFM rule evaluation using manufactured silicon

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2013 DREAMS (DFM Rule EvAluation using Manufactured Silicon) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of DFM (design for manufacturability) rules using the results of logic diagnosis performed on failed ICs. DREAM ... Full text Cite

Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2013 Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to addres ... Full text Cite

Jacobian singularities in optimal power flow problems caused by intertemporal constraints

Conference 45th North American Power Symposium, NAPS 2013 · December 1, 2013 In multi-timestep Optimal Power Flow (OPF) formulations, constraints that are time-dependent such as generator ramp limits and specifically energy storage constraints may cause the Jacobian matrix to become singular as the problem iterates towards the opti ... Full text Cite

Test data analytics - Exploring spatial and test-item correlations in production test data

Conference Proceedings - International Test Conference · December 1, 2013 The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item corre ... Full text Cite

PADRE: Physically-aware diagnostic resolution enhancement

Conference Proceedings - International Test Conference · December 1, 2013 Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite th ... Full text Cite

Strip-and-zone micro-channel liquid cooling of integrated circuits chips with non-uniform power distributions

Conference ASME 2013 Heat Transfer Summer Conf. Collocated with the ASME 2013 7th Int. Conf. on Energy Sustainability and the ASME 2013 11th Int. Conf. on Fuel Cell Science, Engineering and Technology, HT 2013 · December 1, 2013 For a high-power integrated circuit (IC), it is desirable to cool with the liquid micro-channels. However, the non-uniform power distribution of the IC is a great challenge. In this paper, the strip-and-zone strategy is presented. First, the optimal channe ... Full text Cite

Structure-aware high-dimensional performance modeling for analog and mixed-signal circuits

Conference Proceedings of the Custom Integrated Circuits Conference · November 7, 2013 Efficient high-dimensional performance modeling of nanoscale analog and mixed signal (AMS) circuits is extremely challenging. In this paper, we propose a novel structure-aware modeling (SAM) technique. The key idea of SAM is to accurately solve the model c ... Full text Cite

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

Conference Proceedings of the Custom Integrated Circuits Conference · November 7, 2013 On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate ... Full text Cite

Formal verification of phase-locked loops using reachability analysis and continuization

Journal Article Communications of the ACM · October 22, 2013 We present a scalable and formal technique to verify locking time and stability for charge-pump phase-locked loops (PLLs). In contrast to the traditional simulation approach that only validates the PLL at a given operation condition, our proposed technique ... Full text Cite

Referee consensus: A platform technology for nonlinear optimization

Conference ACM International Conference Proceeding Series · August 26, 2013 Electrical current flow within populations of neurons is a fundamental constituent of brain function. The resulting fluctuating magnetic fields may be sampled noninvasively with an array of magnetic field detectors positioned outside the head. This is magn ... Full text Cite

Efficient spatial pattern analysis for variation decomposition via robust sparse regression

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · July 15, 2013 In this paper, we propose a new technique to achieve accurate decomposition of process variation by efficiently performing spatial pattern analysis. We demonstrate that the spatially correlated systematic variation can be accurately represented by the line ... Full text Cite

Automatic clustering of wafer spatial signatures

Conference Proceedings - Design Automation Conference · July 12, 2013 In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically captu ... Full text Cite

Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation

Conference Proceedings - Design Automation Conference · July 12, 2013 A critical problem in pre-Silicon and post-Silicon validation of analog/mixed-signal circuits is to estimate the distribu- tion of circuit performances, from which the probability of failure and parametric yield can be estimated at all circuit configuratio ... Full text Cite

Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data

Conference Proceedings - Design Automation Conference · July 12, 2013 Efficient high-dimensional performance modeling of today's complex analog and mixed-signal (AMS) circuits with large-scale process variations is an important yet challenging task. In this paper, we propose a novel performance modeling algorithm that is ref ... Full text Cite

Erratum: A linearized, low phase noise VCO based 25 GHz PLL with autonomic biasing (IEEE Journal of Solid-State Circuits (2013) 48:5 (1138-1150))

Journal Article IEEE Journal of Solid-State Circuits · June 5, 2013 Full text Cite

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Journal Article IEEE Journal of Solid-State Circuits · May 1, 2013 This paper describes a new approach to low-phase-noise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performan ... Full text Cite

A high-linearity WCDMA/GSM reconfigurable transceiver in 0.13-μm CMOS

Journal Article IEEE Transactions on Microwave Theory and Techniques · January 1, 2013 This paper presents a dual-mode multiband transceiver with DigRF interface implemented in a 0.13-μm CMOS technology. Based on direct conversion architecture, blocks in the transceiver can be configured to simultaneously support wavelength code-division mul ... Full text Cite

Optimal integration of intermittent energy sources using distributed multi-step optimization

Conference IEEE Power and Energy Society General Meeting · December 11, 2012 The integration of renewable energy sources such as wind and solar into the electric power grid is a coveted yet challenging goal. The difficulties arise from the intermittency of the sources, the required increase in transmission capacity, and the lack of ... Full text Cite

Inclusion of inter-temporal constraints into a distributed Newton-Raphson method

Conference 2012 North American Power Symposium, NAPS 2012 · December 10, 2012 Newton-Raphson based methods are widely used for solving Optimal Power Flow (OPF) problems. Convergence can be sensitive to the starting point of the algorithm, the step size, and the condition number of the Jacobian. The inclusion of inter-temporal constr ... Full text Cite

Verify level control criteria for multi-level cell flash memories and their applications Coding and Signal Processing for Non-Volatile Memories

Journal Article Eurasip Journal on Advances in Signal Processing · December 1, 2012 In 1 M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to S ... Full text Cite

Efficient SRAM failure rate prediction via Gibbs sampling

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · November 26, 2012 Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, ... Full text Cite

Modeling local variation of low-frequency noise in MOSFETs via sum of lognormal random variables

Conference Proceedings of the Custom Integrated Circuits Conference · November 26, 2012 In this paper, we investigate the geometry dependence for the local variation of low-frequency noise in MOSFETs via the sum of lognormal random variables. A compact model has been developed and applied to the measured data with excellent match, and therefo ... Full text Cite

Large-scale statistical performance modeling of analog and mixed-signal circuits

Conference Proceedings of the Custom Integrated Circuits Conference · November 26, 2012 The aggressive scaling of IC technology results in large-scale performance variations that cannot be efficiently captured by traditional modeling techniques. This paper presents the recent development of statistical performance modeling and its important a ... Full text Cite

Spatial variation decomposition via sparse regression

Conference ICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology · August 13, 2012 In this paper, we briefly discuss the recent development of a novel sparse regression technique that aims to accurately decompose process variation into two different components: (1) spatially correlated variation, and (2) uncorrelated random variation. Su ... Full text Cite

An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring

Conference Proceedings - Design Automation Conference · July 11, 2012 Full-chip thermal monitoring is an important and challenging issue in today's microprocessor design. In this paper, we propose a new information-theoretic framework to quantitatively model the uncertainty of on-chip temperature variation by differential en ... Full text Cite

Statistical design and optimization for adaptive post-silicon tuning of MEMS filters

Conference Proceedings - Design Automation Conference · July 11, 2012 Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we describe a novel technique of adaptive post-silicon tuning to reliably design MEM ... Full text Cite

A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · April 26, 2012 Thermal issues have become critical roadblocks for the development of advanced chip-multiprocessors (CMPs). In this paper, we introduce a new angle to view transient thermal analysis - based on predicting thermal profile, instead of calculating it. We deve ... Full text Cite

Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2012 Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield est ... Full text Cite

Post-silicon performance modeling and tuning of analog/mixed-signal circuits via bayesian model fusion

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2012 Post-silicon tuning has recently emerged as an important technique to combat large-scale uncertainties (e.g., process variation, device modeling errors, etc) for today's nanoscale circuits. This talk presents a novel Bayesian Model Fusion (BMF) technique f ... Full text Cite

Test cost reduction through performance prediction using virtual probe

Conference Proceedings - International Test Conference · December 1, 2011 The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduct ... Full text Cite

Toward efficient spatial variation decomposition via sparse regression

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2011 In this paper, we propose a new technique to accurately decompose process variation into two different components: (1) spatially correlated variation, and (2) uncorrelated random variation. Such variation decomposition is important to identify systematic v ... Full text Cite

Formal verification of phase-locked loops using reachability analysis and continuization

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2011 We present an approach for verifying locking of charge-pump phase-locked loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behavio ... Full text Cite

Virtual probe: A statistical framework for low-cost silicon characterization of nanoscale integrated circuits

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · December 1, 2011 In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize, and monitor spatially-correlated inter-die and/or intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs ... Full text Cite

Indirect phase noise sensing for self-healing voltage controlled oscillators

Conference Proceedings of the Custom Integrated Circuits Conference · November 9, 2011 The push for higher performance analog/RF circuits in scaled CMOS necessitates self-healing via post-manufacturing tuning. A major challenge with self-healing systems is the efficient design of on-chip sensors that capture the performance of interest. This ... Full text Cite

Bridging design and manufacture of analog/mixed-signal circuits in advanced CMOS

Conference Digest of Technical Papers - Symposium on VLSI Technology · September 16, 2011 We present device and circuit characterization resulting from technology/design co-development to improve the design and manufacture of analog/mixed-signal (AMS) circuits in processors. We introduce I D-based MOSFET transconductance measurements and a new ... Cite

Rethinking memory redundancy: Optimal bit cell repair for maximum-information storage

Conference Proceedings - Design Automation Conference · September 16, 2011 SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unlike the traditional memory repair that attempts to replace all failed bit cell ... Cite

CMOS highly linear direct-conversion transmitter for WCDMA with fine gain accuracy

Journal Article Journal of Semiconductors · August 1, 2011 A highly linear, high output power, 0.13 μm CMOS direct conversion transmitter for wideband code division multiple access (WCDMA) is described. The transmitter delivers 6.8 dBm output power with 38 mA current consumption. With careful design on the resisto ... Full text Cite

Clustering linear discriminant analysis for MEG-based brain computer interfaces.

Journal Article IEEE transactions on neural systems and rehabilitation engineering : a publication of the IEEE Engineering in Medicine and Biology Society · June 2011 In this paper, we propose a clustering linear discriminant analysis algorithm (CLDA) to accurately decode hand movement directions from a small number of training trials for magnetoencephalography-based brain computer interfaces (BCIs). CLDA first applies ... Full text Cite

Task-related MEG source localization via discriminant analysis.

Journal Article Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference · January 2011 To investigate the neural activity corresponding to different cognitive states, it is of great importance to localize the cortical areas that are associated with task-related modulation. In this paper, we propose a novel discriminant pattern source localiz ... Full text Cite

Efficient SRAM failure rate prediction via Gibbs sampling

Conference Proceedings - Design Automation Conference · January 1, 2011 Statistical analysis of SRAM has emerged as a challenging issue because the failure rate of SRAM cells is extremely small. In this paper, we develop an efficient importance sampling algorithm to capture the rare failure event of SRAM cells. In particular, ... Full text Cite

Efficient incremental analysis of on-chip power grid via sparse approximation

Conference Proceedings - Design Automation Conference · January 1, 2011 In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid network is locally updated during circuit design, its response changes locally a ... Full text Cite

Benchmark tests for MOSFET compact models

Chapter · December 1, 2010 It has long been recognized that, apart from computational efficiency and accuracy of fitting experimental data, compact MOS transistor models should exhibit qualitatively correct physical behavior for drain current, terminal charges, noise, and all deriva ... Full text Cite

Surface-potential-based compact model of bulk MOSFET

Chapter · December 1, 2010 We review surface-potential-based approach to compact modeling of bulk MOS transistors and provide introduction to the widely used PSP model jointly developed by the Arizona State University and NXP Semiconductors. The emphasis is on the interplay between ... Full text Cite

A 130nm CMOS direct conversion transmitter for WCDMA

Conference ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings · December 1, 2010 A highly integrated 0.13um CMOS direct conversion transmitter front-end for wide-band code division multiple access (WCDMA) is presented. The transmitter delivers +6.8dBm output power while consuming 39mA. The overall gain can be programmed in 6dB steps ov ... Full text Cite

Finding deterministic solution from underdetermined equation: Large-scale performance variability modeling of analog/RF circuits

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · November 1, 2010 The aggressive scaling of integrated circuit technology results in high-dimensional, strongly-nonlinear performance variability that cannot be efficiently captured by traditional modeling techniques. In this paper, we adapt a novel L0-norm regularization m ... Full text Cite

Bayesian Virtual Probe: Minimizing variation characterizationcost for nanoscale IC technologies via Bayesian inference

Conference Proceedings - Design Automation Conference · September 7, 2010 The expensive cost of testing and characterizing parametric variations is one of the most critical issues for today's nanoscale manufacturing process. In this paper, we propose a new technique, referred to as Bayesian Virtual Probe (BVP), to efficiently me ... Full text Cite

Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression

Conference Proceedings - Design Automation Conference · September 7, 2010 In this paper, we propose a novel multi-mode/multi-corner sparse regression (MSR) algorithm to build large-scale performance models of integrated circuits at multiple working modes and environmental corners. Our goal is to efficiently extract multiple perf ... Full text Cite

Real-time robust signal space separation for magnetoencephalography.

Journal Article IEEE transactions on bio-medical engineering · August 2010 In this paper, we develop a robust signal space separation (rSSS) algorithm for real-time magnetoencephalography (MEG) data processing. rSSS is based on the spatial signal space separation (SSS) method and it applies robust regression to automatically dete ... Full text Cite

Statistical modeling of inter-device correlations with BPV

Journal Article Solid-State Electronics · August 1, 2010 The backward propagation of variance (BPV) technique for statistical modeling has proven to be efficient and effective in practice. In this paper we extend the BPV formalism to explicitly include modeling of the correlations between electrical performances ... Full text Cite

Statistical modeling with the PSP MOSFET model

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · April 1, 2010 PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV statistical modeling of NMOS and PMOS devices is, for the first time, coupled ... Full text Cite

Extensions to backward propagation of variance for statistical modeling

Journal Article IEEE Design and Test of Computers · March 1, 2010 Editor's note: Correlating the statistics of process parameters with the statistics of electrical performance is a vital task in statistical modeling. This article describes a more general form of the backward propagation of variance (BPV) method, a numeri ... Full text Cite

Maximum-information storage system: Concept, implementation and application

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2010 The aggressive technology scaling has made it increasingly difficult to design high-performance, high-density SRAM circuits. In this paper, we propose a new SRAM design methodology that is referred to as maximum-information storage system (MISS). Unlike mo ... Full text Cite

Multi-wafer virtual probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2010 In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian inference is derived to extract a shared mod ... Full text Cite

Large-scale analog/RF performance modeling by statistical regression

Conference ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC · December 1, 2009 In this paper, we introduce several large-scale modeling techniques to analyze the high-dimensional, strongly-nonlinear performance variability observed in nanoscale manufacturing technologies. Our goal is to solve a large number of (e.g., 1044-106) model ... Full text Cite

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2009 In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die variations in nanoscale manufacturing process. VP exploits recent breakthroughs ... Cite

Surface-potential-based MOSFET models with introduction to PSP

Conference 2009 IEEE 10th Annual Wireless and Microwave Technology Conference, WAMICON 2009 · November 18, 2009 We review compact modeling techniques that enable a surface-potential-based approach to modeling MOS transistors. These include symmetric linearization method, an analytical approximation of surface potential and surface-potential-based extrinsic device mo ... Full text Cite

Finding deterministic solution from underdetermined equation: Large-scale performance modeling by least angle regression

Conference Proceedings - Design Automation Conference · November 10, 2009 The aggressive scaling of IC technology results in highdimensional, strongly-nonlinear performance variability that cannot be efficiently captured by traditional modeling techniques. In this paper, we adapt a novel L 1-norm regularization method to address ... Cite

Efficient design-specific worst-case corner extraction for integrated circuits

Conference Proceedings - Design Automation Conference · November 10, 2009 While statistical analysis has been considered as an important tool for nanoscale integrated circuit design, many IC designers would like to know the design-specific worst-case corners for circuit debugging and failure diagnosis. In this paper, we propose ... Cite

Parameter extracttion for the PSP MOSFET model by the combination of genetic and levenberg-marquardt algorithms

Conference IEEE International Conference on Microelectronic Test Structures · July 15, 2009 Based on the combination of the genetic and Levenberg-Marquardt algorithms, a new method is developed to perform both local and global parameter extraction for the PSP MOSFET model. It has been successfully used to extract parameter sets for a 65-nm techno ... Full text Cite

Improved parameter extraction procedure for PSP-based MOS varactor model

Conference IEEE International Conference on Microelectronic Test Structures · July 15, 2009 We present an improved procedure for extracting parasitic capacitance parameters and gate current parameters for MOSYAR, the industry standard MOS varactor model. Our technique is verified against measured data from three technology nodes (180 nm, 130 nm a ... Full text Cite

Efficient statistical analysis of read timing failures in sram circuits

Conference Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 · July 8, 2009 A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for is ... Full text Cite

The new CMC standard compact MOS model PSP: Advantages for RF applications

Conference IEEE Journal of Solid-State Circuits · May 1, 2009 The surface-potential-based compact MOS model PSP is reviewed with special emphasis to features of interest to analog and RF designers. Various aspects of the model are discussed, such as Gummel symmetry, capacitance reciprocity at $VDS = 0 V, parasitic re ... Full text Cite

Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · May 1, 2009 Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufac ... Full text Cite

Benchmark tests for MOSFET compact models with application to the PSP model

Journal Article IEEE Transactions on Electron Devices · January 23, 2009 This paper presents the results of several qualitative "benchmark" tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental d ... Full text Cite

Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · January 1, 2009 Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufac ... Cite

PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations

Journal Article Solid-State Electronics · January 1, 2009 This paper reports recent progress in partially depleted (PD) SOI MOSFET modeling using a surface potential based approach. The new model is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-b ... Full text Cite

SRAM parametric failure analysis

Conference Proceedings - Design Automation Conference · January 1, 2009 With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical performance models with accuracy sufficient to facilitate probability extract ... Full text Cite

Mismatch analysis and statistical design at 65 nm and below

Conference Proceedings of the Custom Integrated Circuits Conference · December 26, 2008 Transistor sizing to control random mismatch is investigated. Input offset voltage of 65nm bulk CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage (Vtn, Vtp) variation effects and compare them with statistical models and Pel ... Full text Cite

Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines

Conference Proceedings of the Custom Integrated Circuits Conference · December 26, 2008 A configurable replica bitline (cRBL) technique for controlling sense-amplifier enable (SAE) timing for small-swing bitline SRAMs is described. Post-silicon selection of a subset of replica bitline driver cells from a statistically designed pool of cells f ... Full text Cite

A nonlinear body resistance model for accurate PD/SOI technology characterization

Conference Proceedings - IEEE International SOI Conference · December 24, 2008 We report a bias-dependent, nonlinear body resistance model suitable for accurate characterization of PD/SOI technology. This model is implemented in the surface potential based SOI MOSFET compact model PSP-SOI and experimentally verified for 65 nm PD/SOI ... Full text Cite

(Invited) the new CMC standard compact MOS model PSP: Advantages for RF applications

Conference Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium · September 22, 2008 First the surface-potential-based compact MOS model, PSP, is introduced. After a discussion of the general advantages of this model, it is benchmarked against measurements from the 45 nm technology node. Finally, we zoom in on the modeling in PSP of two ef ... Full text Cite

Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations

Conference Proceedings - Design Automation Conference · September 17, 2008 The continuous technology scaling brings about high-dimensional performance variations that cannot be easily captured by the traditional response surface modeling. In this paper we propose a new statistical regression (STAR) technique that applies a novel ... Full text Cite

Projection-based piecewise-linear response surface modeling for strongly nonlinear VLSI performance variations

Conference Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008 · August 25, 2008 Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about high-dimensional strongly nonlinear performance variations that cannot be accurately captured by linear or quadratic response surface models. In ... Full text Cite

Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations

Conference IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · June 1, 2008 The large-scale process and environmental variations for today's nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective und ... Full text Cite

Quadratic statistical MAX approximation for parametric yield estimation of analog/RF integrated circuits

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · May 1, 2008 In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering large-scale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed ... Full text Cite

Digital circuit design challenges and opportunities in the era of nanoscale CMOS

Journal Article Proceedings of the IEEE · January 1, 2008 Well-designed circuits are one key ldquoinsulatingrdquo layer between the increasingly unruly behavior of scaled complementary metal-oxide-semiconductor devices and the systems we seek to construct from them. As we move forward into the nanoscale regime, c ... Full text Cite

Adaptive post-silicon tuning for analog circuits: Concept, analysis and optimization

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2007 The well-known Pelgrom model [14] has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area: σ ∼ 1/sqrt(Area). Based on the Pelgrom model, analog devices a ... Full text Cite

Benchmarking the PSP compact model for MOS transistors

Conference IEEE International Conference on Microelectronic Test Structures · September 27, 2007 Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative "benchmark" tests that over the last two years were used to verify the physical behavior ... Full text Cite

Parameterized macromodeling for analog system-level design exploration

Conference Proceedings - Design Automation Conference · August 2, 2007 In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our proposed approach captures a significantly larger analog design space to fac ... Full text Cite

Efficient parametric yield extraction for multiple correlated non-normal performance distributions of analog/RF circuits

Conference Proceedings - Design Automation Conference · August 2, 2007 In this paper we propose an efficient numerical algorithm to estimate the parametric yield of analog/RF circuits with consideration of large-scale process variations. Unlike many traditional approaches that assume Normal performance distributions, the prop ... Full text Cite

A compact model for valence-band electron tunneling current in partially depleted SOI MOSFETs

Journal Article IEEE Transactions on Electron Devices · February 1, 2007 The valence-band electron (EVB) tunneling current in partially depleted silicon-on-insulator (SOI) MOSFETs increases as the gate oxide gets thinner and affects the dynamic behavior of devices and circuits. We present an engineering model of EVB tunneling c ... Full text Cite

PSP-SOI: A surface potential based compact model of partially depleted SOI MOSFETs

Conference Proceedings of the Custom Integrated Circuits Conference · January 1, 2007 This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, Is formulated within the framework of the latest Industry standard bulk MOSFET model PSP. In addition to Its ... Full text Cite

Asymptotic probability extraction for nonnormal performance distributions

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · January 1, 2007 While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via normal distributions. Nonlinear response sur ... Full text Cite

Robust analog/RF circuit design with projection-based performance modeling

Journal Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · January 1, 2007 In this paper, a robust analog design (ROAD) tool for posttuning (i.e., locally optimizing) analog/RF circuits is proposed. Starting from an initial design derived from hand analysis or analog circuit optimization based on simplified models, ROAD extracts ... Full text Cite

Theory and modeling techniques used in the PSP model

Conference 2006 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2006 Technical Proceedings · December 8, 2006 This paper describes theoretical foundation and details of the new compact modeling techniques used in the advanced surface-potential-based compact MOSFET model PSP, jointly developed by the Pennsylvania State University and Philips Research. Specific topi ... Cite

Active on-die suppression of power supply noise

Conference Proceedings of the Custom Integrated Circuits Conference · December 1, 2006 An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% ... Full text Cite

Statistical performance modeling and optimization

Journal Article Foundations and Trends in Electronic Design Automation · December 1, 2006 As IC technologies scale to finer feature sizes, it becomes increasingly difficult to control the relative process variations. The increasing fluctuations in manufacturing processes have introduced unavoidable and significant uncertainty in circuit perform ... Full text Cite

PSP: An advanced surface-potential-based MOSFET model for circuit simulation

Journal Article IEEE Transactions on Electron Devices · September 1, 2006 This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development a ... Full text Cite

A unified nonquasi-static MOSFET model for large-signal and small-signal simulations

Journal Article IEEE Transactions on Electron Devices · September 1, 2006 The spline collocation-based nonquasi-static (NQS) model is further developed to include all regions of operation and small-geometry effects. The new formulation provides a unified (hence consistent) approach to both large-signal and small-signal NQS model ... Full text Cite

Architecture-aware FPGA placement using metric embedding

Conference Proceedings - Design Automation Conference · January 1, 2006 Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new ar-chitecture-aware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from g ... Full text Cite

Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions

Conference Proceedings - Design Automation Conference · January 1, 2006 In this paper we propose a novel projection-based algorithm to estimate the full-chip leakage power with consideration of both inter-die and intra-die process variations. Unlike many traditional approaches that rely on log-Normal approximations, the propos ... Full text Cite

Projection-based performance modeling for inter/intra-die variations

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2005 Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solvi ... Full text Cite

OPERA: Optimization with ellipsoidal uncertainty for robust analog IC design

Conference Proceedings - Design Automation Conference · December 1, 2005 As the design-manufacturing interface becomes increasingly complicated with IC technology scaling, the corresponding process variability poses great challenges for nanoscale analog/RF design. Design optimization based on the enumeration of process corners ... Cite

Modeling interconnect variability using efficient parametric model order reduction

Conference Proceedings -Design, Automation and Test in Europe, DATE '05 · December 1, 2005 Assessing IC manufacturing process fluctuations and their impacts on IC interconnect performance has become unavoidable for modern DSM designs. However, the construction of parametric interconnect models is often hampered by the rapid increase in computati ... Full text Cite

Performance-centering optimization for system-level analog design exploration

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2005 In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog system architectures in the early phases of design; and (2) how to hierarchic ... Full text Cite

SP-SOI: A third generation surface potential based compact SOI MOSFET model

Conference Proceedings of the Custom Integrated Circuits Conference · January 1, 2005 We report the first SOI MOSFET model that takes advantage of the recent progress in bulk MOSFET modeling. The surface-potential-based model is implemented without iterative loops, and includes physical modeling of the moderate inversion region and all smal ... Full text Cite

Unified non-quasi-static MOSFET model for large-signal and small-signal simulations

Conference Proceedings of the Custom Integrated Circuits Conference · January 1, 2005 The spline-collocation-based non-quasi-static model is extended to include small-geometry effects and to enable both small-signal and large-signal simulations. The new NQS model has been implemented into circuit simulators using both SP and PSP models and ... Full text Cite

Correlation-aware statistical timing analysis with non-gaussian delay distributions

Conference Proceedings - Design Automation Conference · January 1, 2005 Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In ... Full text Cite

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · January 1, 2005 The large-scale process and environmental variations for today's nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithm ... Full text Cite

Asymptotic probability extraction for non-normal distributions of circuit performance

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2004 While process variations are becoming more significant with each new IC technology generation, they are often modeled via linear regression models so that the resulting performance variations can be captured via Normal distributions. Nonlinear (e.g. quadra ... Cite

Robust analog/RF circuit design with projection-based posynomial modeling

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD · December 1, 2004 In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance ... Cite

Cost function selection for wavelet-based VBR video traffic smoothing

Journal Article Electronics Letters · November 11, 2004 Variable bit rate (VBR) video traffic exhibits high rate variability, so smoothing algorithms are proposed to smooth video traffic using some cost functions. However, the relationship between cost functions and smoothing performance is not clear. To addres ... Full text Cite

STAC: Statistical timing analysis with correlation

Conference Proceedings - Design Automation Conference · September 20, 2004 Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter variations for sub-100nm technologies to produce an upper bound prediction on timi ... Cite

A frequency relaxation approach for analog/RF system-level simulation

Conference Proceedings - Design Automation Conference · January 1, 2004 The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and simulation approaches have been successfully applied for such purposes (e.g. Simu ... Full text Cite

A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers · December 26, 2003 Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Recent progress has been made for constructing such macromodels, however, their a ... Cite

Noise macromodel for radio frequency integrated circuits

Conference Proceedings -Design, Automation and Test in Europe, DATE · December 1, 2003 Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some model of the noise is represented at the highest levels of abstraction during th ... Full text Cite

Noise macromodel for radio frequency integrated circuits

Behavioral modeling for analog system-level simulation by wavelet collocation method

Journal Article IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing · June 1, 2003 In this paper, we propose a wavelet collocation method with nonlinear companding to generate behavioral models for analog circuits at the system level. During the overall process of circuit modeling, nonlinear function approximation is an Important issue t ... Full text Cite

A frequency separation macromodel for system-level simulation of RF circuits

Conference Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC · January 1, 2003 In this paper, we propose a frequency-separation methodology to generate system-level macromodels for analog and RF circuits. The proposed macromodels are similar in form to those based on Volterra kernel calculations, but are much simpler in terms of char ... Full text Cite

Analog and RF circuit macromodels for system-level analysis

Conference Proceedings - Design Automation Conference · January 1, 2003 Design and validation of mixed-signal integrated systems require system-level model abstractions. Generalized Volterra series based models have been successfully applied for analog and RF component macromodels, but their complexity can sometimes limit thei ... Full text Cite

High-speed clock tree simulation with fast wavelet collocation method

Journal Article Chinese Journal of Electronics · January 1, 2003 In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the followin ... Cite

FECG detection based on blind signal separation

Journal Article Chinese Journal of Biomedical Engineering · October 20, 2002 A new method of blind signal separation was provided to achieve FECG (Fetal ECG) detection. The lead-system characteristic for pregnant ECG signal was studied at first, then an on-line FECG monitoring system was designed. Because the on-line learning algor ... Cite

A wavelet-balance approach for steady-state analysis of nonlinear circuits

Journal Article IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications · May 1, 2002 In this paper, a novel wavelet-balance method is proposed for steady-state analysis of nonlinear circuits. Taking advantage of the superior computational properties of wavelets, the proposed method presents several merits compared with those conventional f ... Full text Cite

Wavelet method for high-speed clock tree simulation

Conference Proceedings - IEEE International Symposium on Circuits and Systems · January 1, 2002 In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the followin ... Cite

A wavelet balance approach for steady-state analysis of nonlinear circuits

Conference ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings · December 1, 2001 In this paper, a novel wavelet balance method is proposed for steady-state analysis of nonlinear circuits. The proposed method presents several merits compared with those conventional frequency domain techniques, First, it has a high convergence rate. Seco ... Full text Cite

Wavelet balance approach for steady-state analysis in nonlinear circuits

Journal Article Tien Tzu Hsueh Pao/Acta Electronica Sinica · June 1, 2001 This paper provides a novel wavelet balance approach for steady-state analysis in nonlinear circuits. Because the proposed simulation algorithm is performed in time domain, it can overcome most of the disadvantages of the frequency domain based methodology ... Cite

Fast wavelet collocation method with nonlinear companding in time domain

Journal Article Tien Tzu Hsueh Pao/Acta Electronica Sinica · May 1, 2001 This paper provides a new method to regulate the step length of FWCM by nonlinear companding in time domain, so that the error distribution can be controlled in circuit simulation. Because the technology of domain transform is used, the step length of FWCM ... Cite

Behavioral modeling of analog circuits by wavelet collocation method

Conference IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers · January 1, 2001 In this paper, we develop a wavelet collocation method with nonlinear companding for behavioral modeling of analog circuits. To construct the behavioral models, the circuit is first partitioned into building blocks and the input-output function of each blo ... Cite